Method of forming a high electron mobility transistor

Patent metadata

Field	Value
Publication number	US-9236464-B2
Application number	US-201414549352-A
Country	US
Kind code	B2
Filing date	Nov 20, 2014
Priority date	Aug 9, 2012
Publication date	Jan 12, 2016
Grant date	Jan 12, 2016

Abstract

A method of forming a high electron mobility transistor may include: forming a second III-V compound layer on a first III-V compound layer, the second III-V compound layer and the first III-V compound layer differing in composition; forming a p-type doped region in the first III-V compound layer; forming an n-type doped region in the second III-V compound layer, the n-type doped region overlying the p-type doped region; forming a source feature over the second III-V compound layer, the source feature overlying the n-type doped region; and forming a gate electrode over the second III-V compound layer, the gate electrode disposed laterally adjacent to the source feature.

First claim

What is claimed is:

1. A method of forming a high electron mobility transistor (HEMT), the method comprising:
forming a second III-V compound layer on a first III-V compound layer, the second III-V compound layer and the first III-V compound layer differing in composition;
forming a p-type doped region in the first III-V compound layer;
forming an n-type doped region in the second III-V compound layer, the n-type doped region overlying the p-type doped region;
forming a source feature over the second III-V compound layer, the source feature overlying the n-type doped region; and
forming a gate electrode over the second III-V compound layer, the gate electrode disposed laterally adjacent to the source feature.

2. The method of claim 1 , wherein the forming the second III-V compound layer on the first III-V compound layer comprises epitaxially growing the second III-V compound layer on the first III-V compound layer.

3. The method of claim 1 , wherein the forming the p-type doped region comprises selectively implanting p-type dopants into the first III-V compound layer through the second first III-V compound layer.

4. The method of claim 3 , wherein the p-type dopants comprise a Group II element.

5. The method of claim 3 , wherein the p-type dopants comprise magnesium, calcium, beryllium or zinc.

6. The method of claim 1 , wherein the forming the n-type doped region comprises selectively implanting n-type dopants into the first III-V compound layer and the second III-V compound layer.

7. The method of claim 6 , wherein the n-type dopants comprise a Group IV element.

8. The method of claim 6 , wherein the n-type dopants comprise silicon or oxygen.

9. The method of claim 1 , wherein the n-type doped region comprises a peak concentration having a distance D 2 away from an interface between the first III-V compound layer and the second III-V compound layer, the distance D 2 being less than about 50 nm.

10. The method of claim 1 , wherein the p-type doped region comprises a peak concentration having a distance D 1 away from an interface between the first III-V compound layer and the second III-V compound layer, the distance D 1 is in a range from about 50 nm to about 350 nm.

11. A method of forming a high electron mobility transistor (HEMT), the method comprising:
selectively implanting p-type dopants into a first III-V compound layer through a second III-V compound layer disposed over the first III-V compound layer;
selectively implanting n-type dopants into the second III-V compound layer and the first III-V compound layer;
annealing implanted p-type dopants and n-type dopants in the second III-V compound layer and the first III-V compound layer;
forming a source feature and a drain feature on the second III-V compound layer; and
forming a gate electrode over the second III-V compound layer between the source feature and the drain feature.

12. The method of claim 11 , wherein the annealing comprises annealing in an environment comprising nitrogen.

13. The method of claim 11 , wherein the selectively implanting p-type dopants comprises:
forming a photoresist layer over the second III-V compound layer;
forming an opening in the photoresist layer, the opening exposing a portion of the second III-V compound layer; and
implanting the p-type dopants through the opening and the exposed portion of the second III-V compound layer into the first III-V compound layer.

14. The method of claim 11 , wherein the selectively implanting n-type dopants comprises implanting the n-type dopants in a region of the second III-V compound layer and the first III-V compound layer overlying the implanted p-type dopants.

15. The method of claim 11 , wherein the source feature and the drain feature are free of Au and comprise Ti, Co, Ni, W, Pt, Ta, Pd, Mo, Al or TiN.

16. The method of claim 11 , wherein the first III-V compound layer and the second III-V compound layer differ in composition, and wherein a carrier channel is located in the first III-V compound layer along an interface between the first III-V compound layer and the second III-V compound layer.

17. A method of forming a high electron mobility transistor (HEMT), the method comprising:
forming a gallium nitride (GaN) layer on a substrate;
forming an aluminum gallium nitride (AlGaN) layer on the GaN layer;
forming a source feature and a drain feature spaced apart from each other and on the AlGaN layer;
forming an n-type doped region underlying each source feature and drain feature in the AlGaN layer;
forming a p-type doped region underlying each n-type doped region in the GaN layer; and
forming a gate electrode over a portion of the AlGaN layer between the source feature and the drain feature.

18. The method of claim 17 , wherein the forming the AlGaN layer comprises epitaxially growing the AlGaN layer on the GaN layer.

19. The method of claim 17 , wherein the forming the n-type doped region comprises selectively implanting n-type dopants into the AlGaN layer and the GaN layer.

20. The method of claim 17 , wherein the forming the p-type doped region comprises selectively implanting p-type dopants into the GaN layer.

Assignees

• Taiwan Semiconductor Mfg

Inventors

• Chiang Chen-Hao
• Chen Chi-Ming
• Yu Chung-Yi
• Liu Po-Chun
• Chiu Han-Chin

Classifications

• H10D62/8503

  Nitride Group III-V materials, e.g. AlN or GaN · CPC title

• H10D62/161

  of FETs having Schottky gates · CPC title

• H10D30/4755

  having wide bandgap charge-carrier supplying layers, e.g. modulation doped HEMTs such as n-AlGaAs/GaAs HEMTs · CPC title

• H10D30/015 Primary

  of FETs having heterojunction interface channels or heterojunction gate electrodes, e.g. HEMT · CPC title

• H10D30/4735 Primary

  having delta-doped or planar-doped donor layers · CPC title