Package-on-package stacked microelectronic structures

Patent metadata

Field	Value
Publication number	US-10211182-B2
Application number	US-201414649104-A
Country	US
Kind code	B2
Filing date	Jul 7, 2014
Priority date	Jul 7, 2014
Publication date	Feb 19, 2019
Grant date	Feb 19, 2019

Abstract

A package-on-package stacked microelectronic structure comprising a pair of microelectronic packages attached to one another in a flipped configuration. In one embodiment, the package-on-package stacked microelectronic structure may comprise a first and a second microelectronic package, each comprising a substrate having at least one package connection bond pad formed on a first surface of each microelectronic package substrate, and each having at least one microelectronic device electrically connected to the each microelectronic package substrate first surface, wherein the first and the second microelectronic package are connected to one another with at least one package-to-package interconnection structure extending between the first microelectronic package connection bond pad and the second microelectronic package connection bond pad.

First claim

The invention claimed is:

1. A package-on-package stacked microelectronic structure, comprising:
a first microelectronic package, comprising a substrate having a first surface and a second surface opposite the first surface, and at least one package connection bond pad formed on the microelectronic package substrate first surface, and having at least one microelectronic device electrically connected to the first microelectronic package substrate first surface;
a second microelectronic package, comprising a substrate having a first surface and a second surface opposite the first surface, and at least one package connection bond pad formed on each second microelectronic package substrate first surface, and having at least one microelectronic device electrically connected to the second microelectronic package substrate first surface, and having at least two microelectronic devices electrically connected to the second microelectronic package substrate second surface, the at least two microelectronic devices co-planar with one another on the second microelectronic package substrate second surface, and the at least two microelectronic devices electrically coupled to the at least one microelectronic device of the second microelectronic package by conductive routes through the second microelectronic package substrate, wherein a first of the conductive routes couples a first microelectronic device of the at least two microelectronic devices to a microelectronic device of the at least one microelectronic device, and a second of the conductive routes couples a second microelectronic device of the at least two microelectronic devices to the microelectronic device of the at least one microelectronic device; and
at least one package-to-package interconnection structure extending between the first microelectronic package connection bond pad and the second microelectronic package connection bond pad.

2. The package-on-package stacked microelectronic structure of claim 1 , further including an encapsulation material disposed between the first microelectronic package substrate first surface and the second microelectronic package substrate first surface.

3. The package-on-package stacked microelectronic structure of claim 1 , wherein at least one of the first microelectronic package microelectronic device and the second microelectronic package microelectronic device is attached to its respective substrate with a plurality of interconnects in a flip-chip configuration.

4. The package-on-package stacked microelectronic structure of claim 3 , further including at least one of a first underfill material disposed between the first microelectronic package microelectronic device and the first microelectronic package substrate, and a second underfill material disposed between the second microelectronic package microelectronic device and the second microelectronic package substrate.

5. The package-on-package stacked microelectronic structure of claim 1 , wherein at least one of the first microelectronic package microelectronic device and the second microelectronic package microelectronic device is attached to its respective substrate with a plurality of wirebonds.

6. The package-on-package stacked microelectronic structure of claim 1 , wherein a back surface of the first microelectronic package microelectronic device is attached to a back surface of the second microelectronic package microelectronic device with an adhesive material.

7. The package-on-package stacked microelectronic structure of claim 1 , wherein the first microelectronic package substrate includes a second surface and the second microelectronic package substrate includes a second surface, and further including a plurality of external bond pads in or on at least one of the first microelectronic package substrate second surface and the second microelectronic package substrate second surface.

8. A method of forming a package-on-package stacked microelectronic structure, comprising:
forming a first microelectronic package, comprising a substrate having a first surface and at least one package connection bond pad formed on each microelectronic package substrate first surface; electrically connecting at least one first microelectronic device to the microelectronic package substrate first surface;
forming a second microelectronic package, comprising a substrate having a first surface and at least one package connection bond pad formed on each microelectronic package substrate first surface;
electrically connecting at least one second microelectronic device to the second microelectronic package substrate first surface;
electrically connecting at least one third microelectronic device and one fourth microelectronic device to the second microelectronic package substrate second surface, the at least one third and one fourth microelectronic devices co-planar with one another on the second microelectronic package substrate second surface, and the at least one third and one fourth microelectronic devices electrically coupled to the at least one second microelectronic device of the second microelectronic package by conductive routes through the second microelectronic package substrate, wherein a first of the conductive routes couples a first microelectronic device of the at least one third and one fourth microelectronic devices to a microelectronic device of the at least one second microelectronic device, and a second of the conductive routes couples a second microelectronic device of the at least one third and one fourth microelectronic devices to the microelectronic device of the at least one second microelectronic device;
orienting the second microelectronic package first surface to face the first microelectronic package first surface; and
forming at least one package-to-package interconnection structure between the first microelectronic package connection bond pad and the second microelectronic package connection bond pad.

9. The method of claim 8 , wherein forming at least one package-to-package interconnection structure between the first microelectronic package connection bond pad and the second microelectronic package connection bond pad comprises forming a package interconnection material bump on its respective first microelectronic package connection bond pad, forming a package interconnection material bump on the second microelectronic package connection bond pad, and attaching the first microelectronic package interconnection material bump with the second microelectronic package interconnection material bump.

10. The method of claim 9 , wherein forming the package interconnection material bump on its respective first microelectronic package connection bond pad, forming the package interconnection material bump on the second microelectronic package connection bond pad, and attaching the first microelectronic package interconnection material bump with the second microelectronic package interconnection material bump comprises forming a package interconnection solder bump on its respective first microelectronic package connection bond pad, forming the package interconnection solder bump on the second microelectronic package connection bond pad, and reflowing the first microelectronic package interconnection solder bump with the second microelectronic package interconnection solder bump.

11. The method of claim 8 , further including disposing an encapsulation material between the first microelectronic package substrate first surface and the second microelectronic package substrate first surface.

12. The method of claim 8 , wherein electrically connecting the first microelectronic device to the microelectronic package substrate first surface comprises electric

Assignees

• Intel Ip Corp

Inventors

• Meyer Thorsten
• Ofner Gerald

Classifications

• H05K1/11

  Printed elements for providing electric connections to or between printed circuits · CPC title

• H05K2201/10515

  Stacked components · CPC title

• H10W90/754

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/734

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/732

  between stacked chips · CPC title