Semiconductor device with modified current distribution

Patent metadata

Field	Value
Publication number	US-9559086-B2
Application number	US-201514726005-A
Country	US
Kind code	B2
Filing date	May 29, 2015
Priority date	May 29, 2015
Publication date	Jan 31, 2017
Grant date	Jan 31, 2017

Abstract

Semiconductor devices having modified current distribution and methods of forming the same are described herein. As an example, a memory die in contact with a logic die can be configured to draw a sum amount of current from a current source. The memory die can include a plurality of through-substrate vias (TSVs) formed in the memory die and configured to provide the sum amount of current to the memory die from the current source. The memory die can include at least two interconnection contacts associated with a first TSV closer to the current source that are not connected. The memory die can include an electrical connection between at least two interconnection contacts associated with a second TSV that is further in distance from the current source than the first TSV.

First claim

What is claimed is:

1. A semiconductor device, comprising:
a logic die;
a memory die in contact with the logic die and configured to draw a sum amount of current from a current source, wherein the memory die includes:
a plurality of through-substrate vias (TSVs) formed in the memory die to provide the sum amount of current to the memory die from the current source, wherein each of the plurality of TSVs are configured to provide a portion of the sum amount of current to the memory die from the current source;
at least two interconnection contacts associated with a first TSV closer to the current source that are not connected; and
an electrical connection between at least two interconnection contacts associated with a second TSV that is further in distance from the current source than the first TSV.

2. The semiconductor device of claim 1 , wherein a resistance between the at least two interconnection contacts associated with the first TSV is greater than a resistance of the electrical connection.

3. The semiconductor device of claim 1 , wherein the sum amount of current is provided to on-die circuitry through a power bus.

4. The semiconductor device of claim 1 , wherein:
the sum amount of current drawn by the memory die is divided among the plurality of TSVs; and
conductive lines formed according to a semiconductor process are sized and connected to maintain a current through each of the plurality of TSVs under a particular threshold current.

5. The semiconductor device of claim 4 , wherein the particular threshold current is less than 13 mA current.

6. The semiconductor device of claim 1 , wherein the first TSV is coupled to on-die circuitry via interconnection contacts.

7. The semiconductor device of claim 1 , wherein an additional memory die is stacked on the memory die, wherein an additional plurality of TSVs extend through the additional memory die and align to at least a portion of the plurality of TSVs that extend through the memory die.

8. The semiconductor device of claim 7 , wherein:
at least two interconnection contacts associated with a first set of interconnection contacts associated with a first set of TSVs of the plurality of TSVs and a second set of interconnection contacts associated with a second set of TSVs of the additional plurality of TSVs that are a closer physical distance to the current source are not connected; and
a third set of interconnection contacts associated with a third set of TSVs of the plurality of TSVs and a fourth set of interconnection contacts associated with a fourth set of TSVs of the additional plurality of TSVs are a further distance from the current source than the first set are connected.

9. The semiconductor device of claim 8 , wherein a width of an electrical connection between a TSV of the additional plurality of TSVs is narrower than a TSV further from the current source.

10. A semiconductor device comprising:
a logic die;
a memory die in contact with the logic die and configured to draw an amount of current from a current source; and
a plurality of through-substrate vias (TSVs) formed in the memory die and configured to provide the amount of current to the memory die from the current source;
a first conductive line between:
a first TSV having a first distance to the current source and associated with the plurality of TSVs; and
a circuit of the memory die;

wherein the first conductive line has a narrower width than a second conductive line connecting to a second TSV a further physical distance from the current source.

11. The semiconductor device of claim 10 , wherein a width of a conductive line of the plurality of TSVs is dependent on a distance in relation to the current source.

12. The semiconductor device of claim 11 , wherein a width of a conductive line of a TSV of the plurality of TSVs increases as a distance from the current source increases.

13. The semiconductor device of claim 10 , wherein a length and a width of the first conductive line is fabricated such that a resistance of the first conductive line is equivalent to a resistance of the second conductive line.

14. The semiconductor device of claim 10 , wherein a portion of the amount of current through each of the plurality of TSVs is less than 13 mA.

15. The semiconductor device of claim 10 , wherein:
the first TSV is closest to the current source; and
the second TSV is second closest to the current source;
wherein:
the first conductive line has a narrowest width; and
the second conductive line has a second narrowest width.

16. The semiconductor device of claim 15 , wherein:
a third TSV of the plurality of TSVs is third closest to the current source;
a fourth TSV is fourth closest to the current source;
a fifth TSV is fifth closest to the current source; and
a sixth TSV is sixth closest;
wherein:
a conductive line of the third TSV has a third narrowest width;
a conductive line of the fourth TSV has a fourth narrowest width;
a conductive line of the fifth TSV has a fifth narrowest width; and
a conductive line of the sixth TSV has a sixth narrowest width.

17. A method of forming a semiconductor device, comprising:
forming at least two interconnection contacts associated with a first through substrate via (TSV) closer to a current source that are not connected; and
forming an electrical connection between at least two interconnection contacts associated with a second TSV further from the current source than the first TSV.

18. The method of claim 17 , wherein the at least two interconnection contacts associated with the first TSV have greater resistance between the at least two interconnection contacts than the electrical connection between the at least two interconnection contacts associated with the second TSV.

19. The method of claim 17 , wherein:
the first TSV and the second TSV are associated with a memory die stacked on top of a lower memory die; and
the memory die is further from the current source than the lower memory die.

20. The method of claim 19 , wherein interconnection contacts associated with a third TSV that provides current to the first TSV and is associated with the lower memory die are aligned and interconnected.

21. A method of forming a semiconductor device, comprising:
forming a first conductive line between a first through substrate via (TSV) and circuitry of a memory die that couples the first TSV and the circuitry, wherein the first conductive line is a first width; and
forming a second conductive line between a second TSV and the circuitry that couples the second TSV and the circuitry, wherein the second conductive line is a second width; and
connecting a current source to the first TSV and the second TSV;
wherein:
the first TSV is closer to the current source than the second TSV; and
the first width is narrower than the second width.

22. The method of claim 21 , comprising a plurality of TSVs within the memory die to provide a total amount of current from the current source to the memory die through the plurality of TSVs.

23. The method of claim 22 , comprising forming a plurality of conductive lines between each of the plurality of TSVs and the circuitry, wherein a width of each of the plurality of conductive lines is formed based on a distance from the current source.

24. The method of claim 23 , wherein a width associated with a conductive line is formed more narrow when closer to the current source and wider when further from the

Assignees

• Micron Technology Inc

Inventors

• Mei Shizhong
• Wong Victor
• Wright Jeffrey P

Classifications

• H10W20/212

  Top-view shapes or dispositions, e.g. top-view layouts of the vias · CPC title

• H10W90/794

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/724

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/722

  between stacked chips · CPC title

• H10W90/721

  of bump connectors · CPC title