Chip stacked package structure and electronic device

Patent metadata

Field	Value
Publication number	US-9349708-B2
Application number	US-201514729316-A
Country	US
Kind code	B2
Filing date	Jun 3, 2015
Priority date	Jun 5, 2014
Publication date	May 24, 2016
Grant date	May 24, 2016

Abstract

A chip stacked package structure includes a first chip and a second chip, where the second chip is stacked with the first chip and the second chip includes a package layer and a first routing layer, where the package layer includes at least two dies and an attaching part configured to attach the at least two dies, where the attaching part is provided with multiple vias, with a part of vias in the multiple vias disposed at an outer periphery of the at least two dies, and the other part of vias in the multiple vias disposed between the at least two dies, and the first routing layer electrically connects the at least two dies; where the package layer is located between the first routing layer and the first chip, an electrically conductive material is provided in the multiple vias.

First claim

What is claimed is:

1. A chip stacked package structure, wherein the chip stacked package structure comprises:
a first chip; and
a second chip, stacked with the first chip, wherein the second chip comprises:
a package layer, wherein the package layer comprises at least two dies and an attaching part configured to attach the at least two dies, wherein the attaching part is provided with multiple vias, a first part of vias in the multiple vias are disposed at a periphery of the at least two dies, and a second part of vias in the multiple vias are disposed between the at least two dies; and
a first routing layer, electrically connecting the at least two dies; wherein
the package layer is located between the first routing layer and the first chip, an electrically conductive material is disposed in the multiple vias, and the electrically conductive material electrically connects the first routing layer and the first chip, so that the first chip is electrically connected to at least one die of the at least two dies, and
the first part of vias surrounds the at least two dies and an area located between the at least two dies, and the second part of vias is located within the area.

2. The chip stacked package structure according to claim 1 , wherein the attaching part is specifically a package part configured to package the at least two dies.

3. The chip stacked package structure according to claim 1 , wherein the attaching part comprises a package part and at least one via module, wherein the at least one via module is provided with the multiple vias, and the package part is configured to package the at least one via module and the at least two dies.

4. The chip stacked package structure according to claim 3 , wherein the at least one via module is specifically a printed circuit board bar or a through silicon via module.

5. The chip stacked package structure according to claim 1 , wherein the second chip further comprises a second routing layer, wherein the second routing layer is disposed between the package layer and the first chip, and the second routing layer electrically connects the first chip and the electrically conductive material.

6. The chip stacked package structure according to claim 1 , wherein the first chip is a memory chip, a silicon die, a flip chip package, or a passive device.

7. The chip stacked package structure according to claim 1 , wherein the first chip has a same structure as the second chip.

8. The chip stacked package structure according to claim 1 , wherein the first chip is electrically connected to each die of the at least two dies by the electrically conductive material provided in at least two vias of the multiple vias.

9. An electronic device, wherein the electronic device comprises:
a circuit board; and
a chip stacked package that is disposed on the circuit board, wherein the chip stacked package structure comprises:
a first chip; and
a second chip, stacked with the first chip, wherein the second chip comprises:
a package layer, wherein the package layer comprises at least two dies and an attaching part configured to attach the at least two dies, wherein the attaching part is provided with multiple vias, a first part of vias in the multiple vias are disposed at a periphery of the at least two dies, and a second part of vias in the multiple vias are disposed between the at least two dies; and
a first routing layer, electrically connecting the at least two dies; wherein
the package layer is located between the first routing layer and the first chip, an electrically conductive material is disposed in the multiple vias, and the electrically conductive material electrically connects the first routing layer and the first chip, so that the first chip is electrically connected to at least one die of the at least two dies;
wherein the second chip is located between the first chip and the circuit board, and
the first part of vias surrounds the at least two dies and an area located between the at least two dies, and the second part of vias is located within the area.

10. The electronic device according to claim 9 , wherein the electronic device further comprises a substrate that is disposed between the circuit board and the second chip and electrically connects the circuit board and the second chip.

11. The electronic device according to claim 9 , wherein the attaching part is specifically a package part configured to package the at least two dies.

12. The electronic device according to claim 9 , wherein the attaching part comprises a package part and at least one via module, wherein the at least one via module is provided with the multiple vias, and the package part is configured to package the at least one via module and the at least two dies.

13. The electronic device according to claim 12 , wherein the at least one via module is specifically a printed circuit board bar or a through silicon via module.

14. The electronic device according to claim 9 , wherein the second chip further comprises a second routing layer, wherein the second routing layer is disposed between the package layer and the first chip, and the second routing layer electrically connects the first chip and the electrically conductive material.

15. The electronic device according to claim 9 , wherein the first chip is a memory chip, a silicon die, a flip chip package, or a passive device.

16. The electronic device according to claim 9 , wherein the first chip has a same structure as the second chip.

17. The electronic device according to claim 9 , wherein the first chip is electrically connected to each die of the at least two dies by the electrically conductive material provided in at least two vias of the multiple vias.

Assignees

• Huawei Tech Co Ltd

Inventors

• Fu Huili
• Zhang Xiaodong

Classifications

• H10W90/724

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/722

  between stacked chips · CPC title

• H10W90/701

  characterised by the relative positions of pads or connectors relative to package parts · CPC title

• H10W90/22

  the stacked chips being on both top and bottom sides of a package substrate, interposer or RDL · CPC title

• H10W90/20

  Configurations of stacked chips · CPC title