Monolithically integrated chip including active electrical components and passive electrical components with chip edge stabilization structures

Patent metadata

Field	Value
Publication number	US-10199372-B2
Application number	US-201715631006-A
Country	US
Kind code	B2
Filing date	Jun 23, 2017
Priority date	Jun 23, 2017
Publication date	Feb 5, 2019
Grant date	Feb 5, 2019

Abstract

An integrated circuit device including a chip die having a first area with a first thickness surrounding a second area with a second thickness, the first thickness is greater than the second thickness, the chip die having a front-side and a back-side, at least one passive electrical component provided at least one of in or over the chip die in the first area on the front-side, and at least one active electrical component provided at least one of in or over the chip die in the second area on the front-side.

First claim

What is claimed is:

1. An integrated circuit device, comprising:
a chip die having a first area with a first thickness surrounding a second area with a second thickness, the first thickness is greater than the second thickness, the chip die having a front-side and a back-side;
at least one passive electrical component provided at least one of in or over the chip die in the first area on the front-side; and
at least one active electrical component provided at least one of in or over the chip die in the second area on the front-side.

2. The integrated circuit device of claim 1 , further comprising a support layer disposed on or over the chip die in the second area on the back-side in a direction away from the front-side.

3. The integrated circuit device of claim 2 ,
wherein the thickness of the support layer is at least 1 μm.

4. The integrated circuit device of claim 2 ,
wherein the support layer comprises a metal layer.

5. The integrated circuit device of claim 4 ,
wherein the metal layer comprises copper.

6. The integrated circuit device of claim 4 ,
wherein the metal layer is electrically coupled to at least one of the at least one active electrical component or the at least one passive electrical component.

7. The integrated circuit device of claim 1 ,
wherein the at least one passive electrical component is at least one deep trench capacitor.

8. The integrated circuit device of claim 7 ,
wherein a depth of the at least one deep trench capacitor ranges from 20 μm to 50 μm.

9. The integrated circuit device of claim 1 ,
wherein the at least one active electrical component is at least one power transistor.

10. The integrated circuit device of claim 1 ,
wherein the second thickness ranges from 2 μm to 20 μm.

11. The integrated circuit device of claim 1 ,
wherein the first thickness ranges from 10 μm to 200 μm.

12. The integrated circuit device of claim 1 ,
wherein the chip die in the first area comprises a perimeter of the chip die.

13. An integrated circuit device, comprising:
a chip die having a front-side and a back-side opposite the front-side, the chip die comprising a first portion having a first thickness and a second portion having a second thickness, wherein the first thickness is greater than the second thickness and the first thickness and the second thickness are determined between the front-side of the chip die and the back-side of the chip die, the chip die comprising at least one recess in the back-side of the chip die, the at least one recess defined at least by a side wall and a top wall, the side wall comprising at least a part of the first portion and the top wall comprising at least a part of the second portion;
at least one active electrical component formed at least one of in or over the top wall from the front-side of the chip die; and
at least one passive electrical component formed at least one of in or over the side wall from the front-side of the chip die.

14. The integrated circuit device of claim 13 , further comprising a support layer disposed in the at least one recess.

15. The integrated circuit device of claim 14 ,
wherein the support layer comprises a metal layer.

16. The integrated circuit device of claim 15 ,
wherein the metal layer is electrically coupled to at least one of the at least one active electrical component or the at least one passive electrical component.

17. The integrated circuit device of claim 15 ,
wherein the metal layer comprises porous copper.

18. The integrated circuit device of claim 13 ,
wherein the at least one passive electrical component is at least one deep trench capacitor.

19. The integrated circuit device of claim 18 ,
wherein a depth of the at least one deep trench capacitor substantially ranges from 20 μm to 50 μm.

20. The integrated circuit device of claim 13 ,
wherein the at least one active electrical component is at least one transistor.

21. The integrated circuit device of claim 13 ,
wherein a thickness of the top wall ranges from 2 μm to 20 μm.

22. The integrated circuit device of claim 13 ,
wherein a thickness of the side wall ranges from 10 μm to 200 μm.

23. The integrated circuit device of claim 13 ,
wherein a depth of the at least one recess ranges from 10 μm to 190 μm.

24. The integrated circuit device of claim 13 ,
wherein a width of the side wall ranges from 1 μm to 1 cm.

25. The integrated circuit device of claim 13 ,
wherein the side wall comprises an edge of the chip die.

Assignees

• Infineon Technologies Ag

Inventors

• Muri Ingo
• Moder Iris
• Hellmund Oliver
• Baumgartl Johannes
• Saenger Annette
• Eichinger Barbara
• Sommer Doris
• Ludwig Jacob Tillmann

Classifications

• H10W44/601

  Capacitive arrangements (H10W44/20 takes precedence) · CPC title

• H10W20/023

  the interconnections being through-semiconductor vias · CPC title

• H10W20/20

  Interconnections within wafers or substrates, e.g. through-silicon vias [TSV] · CPC title

• H01L21/76898

  Electricity · mapped topic

• H01L27/0629 Primary

  Electricity · mapped topic