Methods for fabricating high-density integrated circuit devices

Patent metadata

Field	Value
Publication number	US-9547740-B2
Application number	US-201414584786-A
Country	US
Kind code	B2
Filing date	Dec 29, 2014
Priority date	May 5, 2011
Publication date	Jan 17, 2017
Grant date	Jan 17, 2017

Abstract

An integrated circuit device having a plurality of lines is described in which the widths of the lines, and the spacing between adjacent lines, vary within a small range which is independent of variations due to photolithographic processes, or other patterning processes, involved in manufacturing the device. A sequential sidewall spacer formation process is described for forming an etch mask for the lines, which results in first and second sets of sidewall spacers arranged in an alternating fashion. As a result of this sequential sidewall spacer process, the variation in the widths of the lines across the plurality of lines, and the spacing between adjacent lines, depends on the variations in the dimensions of the sidewall spacers. These variations are independent of, and can be controlled over a distribution much less than, the variation in the size of the intermediate mask element caused by the patterning process.

First claim

The invention claimed is:

1. An article of manufacture comprising:
a machine readable data storage medium storing in a non-transitory manner a plurality of software code portions defining logic for selecting a design entry for an integrated circuit from a library including a plurality of design entries, entries in the library including specifications of particular cells in a computer readable description language, at least one entry in the library comprising:
a specification for a mask element having a single edge for fabricating an entire plurality of lines of a second material to be grown epitaxially on a first material layer within trenches at locations defined by successive formation against the single edge of first sidewall spacers alternating with second sidewall spacers and removal of the first sidewall spacers; and
a specification for a layout comprising the plurality of lines of the second material.

2. The article of manufacture of claim 1 , wherein the second material and the first material layer are the same material.

3. The article of manufacture of claim 1 , wherein the layout further comprises a transistor formed in a particular one of the lines,
and wherein the at least one entry in the library further comprises a specification for an additional mask layer specifying an additional mask element for defining a gate conductor over the particular line.

4. The article of manufacture of claim 1 , wherein the at least one entry in the library further comprises a specification for an additional mask layer specifying an additional mask element for defining gate conductors oriented orthogonally to the lines.

5. The article of manufacture of claim 1 , wherein lines in the plurality of lines have substantially congruent shapes.

6. The article of manufacture of claim 1 , wherein adjacent lines in the plurality of lines are separated from one another in a direction normal to the single edge of the mask element.

7. The article of manufacture of claim 1 , wherein the single edge of the mask layer is aligned with an edge of a particular line in the plurality of lines.

8. The article of manufacture of claim 1 , wherein the single edge of the mask layer has a contour representative of shapes of the entire plurality of lines.

9. The article of manufacture of claim 1 , wherein the single edge of the mask layer has a contour representative of shapes of each of the plurality of lines.

10. The article of manufacture of claim 1 , wherein lines in the plurality of lines have substantially the same width.

11. The article of manufacture of claim 1 , wherein adjacent lines in the plurality of lines are separated by substantially the same separation width across the plurality of lines.

12. The article of manufacture of claim 1 , wherein the lines in the plurality of lines have a width that varies across the plurality of lines by less than 10%.

13. The article of manufacture of claim 1 , wherein the lines in the plurality of lines have a width less than or equal to 15 nm.

14. The article of manufacture of claim 1 ,
wherein the mask element further has a second single edge for fabricating an entire second plurality of lines of the second material to be grown epitaxially on the first material layer within trenches at locations defined by successive formation against the second single edge of third sidewall spacers alternating with fourth sidewall spacers and removal of the third sidewall spacers,
and wherein the layout further comprises the second plurality of lines of the second material.

15. The article of manufacture of claim 14 ,
wherein the layout is such that:
the first plurality of lines is separated from the second plurality of lines by a minimum spacing at least twice a width of a particular line in the first plurality of lines;
each line in the first plurality of lines has a first line width roughness and a first line edge roughness less than the first line width roughness;
each line in the second plurality of lines has a second line width roughness and a second line edge roughness less than the second line width roughness; and
all the lines in the first plurality of lines have a longitudinal curvature different from each of the lines in the second plurality of lines.

Assignees

• Synopsys Inc

Inventors

• Moroz Victor
• Lin Xi-Wei

Classifications

• H10P50/695 Primary

  characterised by the process involved to create the mask, e.g. lift-off masks or sidewalls or to modify the mask · CPC title

• G06F30/39 Primary

  Circuit design at the physical level (physical level design for reconfigurable circuits G06F30/347) · CPC title

• G06F17/5068 Primary

  Physics · mapped topic

• H01L21/3086

  Electricity · mapped topic

• H10P76/00 Primary

  Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography · CPC title