Integrated circuit connection arrangement for minimizing crosstalk

Patent metadata

Field	Value
Publication number	US-10192989-B2
Application number	US-201715853357-A
Country	US
Kind code	B2
Filing date	Dec 22, 2017
Priority date	Feb 20, 2017
Publication date	Jan 29, 2019
Grant date	Jan 29, 2019

Abstract

A semiconductor package includes a leadframe, having perimeter package leads and a ground voltage lead, a bottom semiconductor die flip-chip mounted to the leadframe, and a top semiconductor die. The bottom semiconductor die has a first frontside active layer with first frontside electrical contacts electrically connected to the leadframe, a first backside portion, and a buried oxide layer situated between the first frontside active layer and the first backside portion. The top semiconductor die is mounted to the first backside portion. The first frontside active layer includes a circuit electrically connected to the first backside portion by a backside electrical connection through the buried oxide layer. The first backside portion of the bottom semiconductor die is electrically connected to the ground voltage lead through a first electrical contact of the first frontside electrical contacts to minimize crosstalk.

First claim

What is claimed is:

1. An apparatus, comprising:
a leadframe having perimeter package leads and a ground voltage lead;
a bottom semiconductor die, the bottom semiconductor die being flip-chip mounted to the leadframe, the bottom semiconductor die comprising: i) a first frontside active layer having first frontside electrical contacts electrically connected to the leadframe, ii) a first backside portion, and iii) a buried oxide layer, the buried oxide layer being situated between the first frontside active layer and the first backside portion; and
a top semiconductor die, the top semiconductor die comprising: i) a second frontside, and ii) a second backside, the second backside of the top semiconductor die being mounted to the first backside portion of the bottom semiconductor die;
wherein:
the first frontside active layer of the bottom semiconductor die comprises a circuit electrically connected to the first backside portion by a backside electrical connection through the buried oxide layer;
a first electrical contact of the first frontside electrical contacts is electrically connected to the backside electrical connection; and
the first backside portion of the bottom semiconductor die is electrically connected to the ground voltage lead of the leadframe through the first electrical contact to minimize crosstalk.

2. The apparatus of claim 1 , wherein:
the bottom semiconductor die is a power semiconductor die.

3. The apparatus of claim 1 , wherein:
an electrical contact of the second frontside of the top semiconductor die is electrically coupled to a first set of the perimeter package leads.

4. The apparatus of claim 3 , wherein:
the top semiconductor die is a controller die.

5. The apparatus of claim 1 , wherein:
the circuit of the bottom semiconductor die comprises two or more transistors;
at least one of the two or more transistors is electrically connected to the first frontside electrical contacts of the bottom semiconductor die; and
at least one of the two or more transistors is electrically connected to the first backside portion of the bottom semiconductor die.

6. The apparatus of claim 5 , wherein:
the two or more transistors comprise a high-side transistor and a low-side transistor;
the high-side transistor comprises a high-side source, a high-side drain, and a high-side gate;
the low-side transistor comprises a low-side source, a low-side drain, and a low-side gate; and
the first backside portion of the bottom semiconductor die is electrically connected to the low-side source through the buried oxide layer.

7. The apparatus of claim 6 , wherein:
an electrical contact of the second frontside of the top semiconductor die is electrically connected to one or both of the high-side gate or the low-side gate.

8. The apparatus of claim 7 , wherein:
the electrical contact of the second frontside of the top semiconductor die is electrically connected to the one or both of the high-side gate or the low-side gate through a perimeter package lead of the perimeter package leads of the leadframe.

9. The apparatus of claim 6 , wherein:
the first electrical contact of the first frontside electrical contacts of the bottom semiconductor die is electrically connected to the low-side source.

10. The apparatus of claim 9 , wherein:
a second electrical contact of the first frontside electrical contacts of the bottom semiconductor die electrically couples the low-side drain to the high-side source; and
the second electrical contact is electrically coupled and physically mounted to a phase node lead of the leadframe.

11. The apparatus of claim 10 , wherein:
a third electrical contact of the first frontside electrical contacts of the bottom semiconductor die is electrically coupled to the high-side drain; and
the third electrical contact is electrically coupled and physically mounted to an input voltage node lead of the leadframe.

Assignees

• Silanna Asia Pte Ltd

Inventors

• Tu Shanghui Larry
• Stuber Michael A
• Tasbas Befruz
• Molin Stuart B
• Jiang Raymond

Classifications

• H10W72/884

  Die-attach connectors and bond wires · CPC title

• H10W72/871

  Bond wires and strap connectors · CPC title

• H10W72/926

  Multiple bond pads having different sizes · CPC title

• H10W90/766

  between a chip and a stacked lead frame, conducting package substrate or heat sink · CPC title

• H10W90/761

  of strap connectors · CPC title