Non-volatile memory device and related method of operation

Patent metadata

Field	Value
Publication number	US-8976595-B2
Application number	US-201213526794-A
Country	US
Kind code	B2
Filing date	Jun 19, 2012
Priority date	Jun 21, 2011
Publication date	Mar 10, 2015
Grant date	Mar 10, 2015

Abstract

A nonvolatile memory device comprises a cell array connected to a plurality of bit lines in an all bit line structure, a page buffer circuit connected to the plurality of bit lines, and control logic configured to control the page buffer circuit. The control logic controls the page buffer circuit to sense memory cells corresponding to both even-numbered and odd-numbered columns of a selected page in a first read mode and to sense memory cells corresponding to one of the even-numbered and odd-numbered columns of the selected page in a second read mode. A sensing operation is performed at least twice in the first read mode and once in the second read mode.

First claim

What is claimed is:

1. A nonvolatile memory device comprising:
a cell array connected to a plurality of bit lines in an all bit line structure;
a page buffer circuit connected to the plurality of bit lines; and
control logic configured to control the page buffer circuit,
wherein the control logic controls the page buffer circuit to sense memory cells corresponding to both even-numbered and odd-numbered columns of a selected page in a first read mode and to sense memory cells…

Assignees

• Jeong Jaeyong
• Lee Ju Seok
• Samsung Electronics Co Ltd

Inventors

• Jeong Jaeyong
• Lee Ju Seok

Classifications

• G11C11/5642 Primary

  Physics · mapped topic

• G11C16/26 Primary

  Physics · mapped topic

• G11C16/24

  Physics · mapped topic

• G11C16/3454

  Physics · mapped topic