Semiconductor memory device

Patent metadata

Field	Value
Publication number	US-2016307638-A1
Application number	US-201615195560-A
Country	US
Kind code	A1
Filing date	Jun 28, 2016
Priority date	Sep 16, 2014
Publication date	Oct 20, 2016
Grant date	—

Abstract

According to one embodiment, a semiconductor memory device includes: first and second memory cells; first and second word lines coupled to the first and second memory cells, respectively. When data is read from the first memory cell, first and second voltages are applied to the first word line. A voltage of the second word line varies continuously by a first potential difference with time while the first voltage is applied to the first word line, and the voltage of the first word line varies continuously by a second potential difference with time while the second voltage is applied to the first word line.

First claim

What is claimed is:

1 . A semiconductor memory device comprising:
a first memory cell; a second memory cell adjacent to the first memory cell; a first word line coupled to the first memory cell; and a second word line coupled to the second memory cell, wherein when data is read from the first memory cell, a first voltage and a second voltage different from the first voltage are applied to the first word line, and a voltage applied to the second word line varies continuously by a first potential difference with time while the first voltage is applied to the first word line, and the voltage applied to the second word line varies continuously by a second potential difference different from the first potential difference with time while the second voltage is applied to the first word line.

2 . The device according to claim 1 , wherein the first voltage is lower than the second voltage, and
the first potential difference is larger than the second potential difference.

3 . The device according to claim 1 , wherein the second voltage is lower than the first voltage, and
the second potential difference is larger than the first potential difference.

4 . The device according to claim 1 , further comprising:
a third memory cell coupled to the first word line; and a fourth memory cell adjacent to the third memory cell and coupled to the second word line, wherein when the data held in the first memory cell is read, data held in the third memory cell is also read, data read from the first memory cell at a time when the voltage applied to the second word line varies by a third potential difference is fetched in a sense amplifier, data read from the third memory cell at a time when the voltage applied to the second word line varies by a fourth potential difference is fetched in the sense amplifier, and the third potential difference is different from the fourth potential difference.

5 . The device according to claim 4 , wherein data is read from the second and fourth memory cells before the first and second voltages are applied to the first word line,
the third potential difference depends on the data read from the second memory cell, and the fourth potential difference depends on the data read from the fourth memory cell.

6 . The device according to claim 1 , wherein in a program-verification operation of the first memory cell,
a voltage applied to the first word line and a voltage applied to the second word line vary continuously with time.

7 . The device according to claim 6 , wherein in the program-verification operation, a varying range of the voltage applied to the first word line is different from a varying range of the voltage applied to the second word line.

8 . The device according to claim 7 , wherein in the program-verification operation, at a time, the voltage applied to the second word line is higher than the voltage applied to the first word line.

9 . The device according to claim 8 , further comprising:
a third memory cell adjacent to the second memory cell; and a third word line coupled to the third memory cell, wherein in the program-verification operation of the first memory cell, a fifth voltage is applied to the third word line, and a maximum voltage applied to the second word line is less than or equal to the fifth voltage.

10 . The device according to claim 1 , wherein a data read operation of the first memory cell includes a first read operation and a second read operation,
in the first read operation, a third voltage lower than the first voltage and a fourth voltage lower than the second voltage are applied to the first word line and a constant voltage is applied to the second word line, and in the second read operation, the first and second voltages are applied to the first word line and the voltage of the second word line is changed.

11 . The device according to claim 1 , further comprising:
a third memory cell; and a third word line coupled to the third memory cell, wherein the first word line is arranged between the second word line and the third word line, data is read from the second and third memory cells before the first and second voltages are applied to the first word line, and a voltage applied to the third word line varies continuously by a third potential difference different from the first potential difference and the second potential difference with time while the first voltage is applied to the first word line.

12 . The device according to claim 11 , wherein the first voltage is for determining whether a threshold voltage of the first memory cell is in an erase level.

13 . The device according to claim 1 , wherein the first and second word lines are stacked, and
the voltage of the second word line depends on a layer position in which the second word line is provided.

14 . The device according to claim 1 , further comprising:
a bit line electrically coupled to the second memory cell; a sense amplifier coupled to the sense amplifier; a first block including the first and second memory cells; and a second block discharging the bit line, wherein the first block is arranged between the sense amplifier and the second block, and the bit line is discharged by the sense amplifier and the second block after a data read operation.

15 . The device according to claim 1 , wherein when a threshold level of the second memory cell is higher than that of the first memory cell, the voltage of the second word line is controlled to correct a threshold voltage of the first memory cell.

16 . The device according to claim 15 , wherein when the threshold level of the second memory cell is the same as that of the first memory cell, the voltage of the second word line is controlled to correct the threshold voltage of the first memory cell.

Assignees

• Toshiba Kk

Inventors

• Shirakawa Masanobu
• Futatsuyama Takuya
• Hosono Koji

Classifications

• G11C16/0483

  comprising cells having several storage transistors connected in series · CPC title

• G11C16/3459 Primary

  Circuits or methods to verify correct programming of nonvolatile memory cells · CPC title

• G11C16/26

  Sensing or reading circuits; Data output circuits · CPC title

• G11C11/5642

  Sensing or reading circuits; Data output circuits · CPC title

• G11C16/08

  Address circuits; Decoders; Word-line control circuits · CPC title