Field effect transistor including multiple aspect ratio trapping structures

Patent metadata

Field	Value
Publication number	US-10181526-B2
Application number	US-201715602593-A
Country	US
Kind code	B2
Filing date	May 23, 2017
Priority date	Jun 2, 2016
Publication date	Jan 15, 2019
Grant date	Jan 15, 2019

Abstract

The present disclosure relates to a field-effect transistor and a method of fabricating the same. A field-effect transistor includes a semiconductor substrate including a first semiconductor material having a first lattice constant, and a fin structure on the semiconductor substrate. The fin structure includes a second semiconductor material having a second lattice constant that is different from the first lattice constant. The fin structure further includes a lower portion that is elongated in a first direction, a plurality of upper portions protruding from the lower portion and elongated in a second direction that is different from the first direction, and a gate structure crossing the plurality of upper portions.

First claim

What is claimed is:

1. A field-effect transistor, comprising:
a semiconductor substrate comprising a first semiconductor material having a first lattice constant; and
a fin structure on the semiconductor substrate, the fin structure comprising a second semiconductor material having a second lattice constant that is different from the first lattice constant,
wherein the fin structure comprises:
a lower portion that is elongated in a first direction;
a plurality of upper portions protruding from the lower portion and elongated in a second direction that is different from the first direction; and
a gate structure crossing the plurality of upper portions.

2. The field-effect transistor of claim 1 , wherein the gate structure comprises:
a gate electrode extending in the first direction and crossing the upper portions of the fin structure; and
a gate insulating layer disposed between the gate electrode and the upper portions of the fin structure.

3. The field-effect transistor of claim 2 , further comprising source/drain regions provided in the upper portions of the fin structure on opposite sides of the gate electrode.

4. The field-effect transistor of claim 1 , wherein a height of the lower portion is greater than two times a width, in the second direction, of the lower portion, and
a length, in the first direction, of the lower portion is greater than the height of the lower portion.

5. The field-effect transistor of claim 1 , wherein a width, in the first direction, of the upper portion is smaller than a width, in the second direction, of the lower portion, and
a height of the upper portion is greater than two times the width, in the first direction, of the upper portion.

6. The field-effect transistor of claim 1 , wherein the upper portions extend in the second direction past the lower portion on opposite sides of the lower portion.

7. The field-effect transistor of claim 1 , wherein the lower portion comprises crystal defects, and the upper portions are substantially free of crystal defects.

8. The field-effect transistor of claim 1 , wherein the fin structure is a unitary body, in which an interface is not formed between the lower portion and the upper portions.

9. The field-effect transistor of claim 1 , further comprising a device isolation layer that is in contact with opposing sidewalls of the lower portion that face each other in the second direction.

10. The field-effect transistor of claim 9 , further comprising a first insulating separation pattern that is in contact with opposing sidewalls of the lower portion that face each other in the first direction,
wherein a bottom surface of the first insulating separation pattern is positioned at a lower level relative to the semiconductor substrate than a bottom surface of the fin structure.

11. The field-effect transistor of claim 1 , further comprising a hard mask pattern between the upper portions of the fin structure, wherein the hard mask pattern is in contact with a top surface of the lower portion of the fin structure.

12. The field-effect transistor of claim 11 , further comprising a second insulating separation pattern that is in contact with opposing sidewalls of the upper portions that face each other in the first direction.

13. A field-effect transistor, comprising:
a semiconductor substrate comprising a first semiconductor material having a first lattice constant; and
a double aspect ratio trapping structure on the semiconductor substrate, the double aspect ratio trapping structure comprising a second semiconductor material having a second lattice constant that is different from the first lattice constant,
wherein the double aspect ratio trapping structure further comprises:
a lower fin portion that is elongated in a first direction;
a plurality of upper fin portions protruding from the lower fin portion and elongated in a second direction that is different from the first direction; and
a gate structure crossing the plurality of upper fin portions.

14. The field-effect transistor of claim 13 , wherein a height of the lower fin portion is greater than two times a width, in the second direction, of the lower fin portion.

15. The field-effect transistor of claim 14 wherein a length, in the first direction, of the lower fin portion is greater than the height of the lower fin portion.

16. The field-effect transistor of claim 13 , wherein a width, in the first direction, of the upper fin portion is less than a width, in the second direction, of the lower fin portion, and
a height of each of the plurality of upper fin portions is greater than two times the width, in the first direction, of each of the plurality of upper fin portions.

17. The field-effect transistor of claim 13 , wherein the double aspect ratio trapping structure is a unitary body, in which an interface is not formed between the lower fin portion and the plurality of upper fin portions.

18. The field-effect transistor of claim 13 , further comprising:
a device isolation layer in contact with opposing sidewalls of the lower fin portion that face each other in the second direction.

Assignees

• Cantoro Mirco
• Heo YeonCheol
• Samsung Electronics Co Ltd

Inventors

• Cantoro Mirco
• Heo YeonCheol

Classifications

• H01L29/1054

  Electricity · mapped topic

• H01L29/0657

  Electricity · mapped topic

• H01L27/0886

  Electricity · mapped topic

• H01L29/785

  Electricity · mapped topic

• H01L29/66545

  Electricity · mapped topic