III-V finFETs on silicon substrate

Patent metadata

Field	Value
Publication number	US-8937299-B2
Application number	US-201313967102-A
Country	US
Kind code	B2
Filing date	Aug 14, 2013
Priority date	Mar 13, 2013
Publication date	Jan 20, 2015
Grant date	Jan 20, 2015

Abstract

A method for forming fin field effect transistors includes forming a dielectric layer on a silicon substrate, forming high aspect ratio trenches in the dielectric layer down to the substrate, the high aspect ratio including a height to width ratio of greater than about 1:1 and epitaxially growing a non-silicon containing semiconductor material in the trenches using an aspect ratio trapping process to form fins. The one or more dielectric layers are etched to expose a portion of the fins. A barrier layer is epitaxially grown on the portion of the fins, and a gate stack is formed over the fins. A spacer is formed around the portion of the fins and the gate stack. Dopants are implanted into the portion of the fins. Source and drain regions are grown over the fins using a non-silicon containing semiconductor material.

First claim

What is claimed is:

1. A fin field effect transistor, comprising:
a substrate formed from a monocrystalline silicon or germanium material;
a dielectric layer having trenches formed therein, the dielectric layer having a lower surface present on a first portion of an upper surface of the substrate;
an etch stop layer atop the dielectric layer;
a plurality of parallel fins formed from a III-V material in the trenches and being in contact with a second portion of the upper surface of the substrate that is adjacent and coplanar with the first portion of the upper surface of the substrate, the trenches being initially dimensioned and configured to have a high aspect ratio including a height to width ratio of greater than about 1:1 to enable non-lattice-matched crystalline III-V material to be formed on the substrate, wherein the high aspect ratio trenches provide that the III-V semiconductor is in direct contact with the silicon substrate and is a monocrystalline structure that is relatively defect free, a doped portion of the plurality of parallel fins being positioned above an upper surface of the etch stop layer and an undoped portion of the plurality of parallel fins being positioned below the etch stop layer;
a gate stack including a barrier layer, a gate dielectric and a gate conductor formed transversely to the plurality of parallel fins, wherein the barrier layer is present on a sidewall and upper surface of the doped portion of the plurality of parallel fins; and
raised source and drain regions formed from a III-V material and being in contact with the fins on opposite sides of the gate stack.

2. The transistor as recited in claim 1 , wherein the fins include side wall spacers about a top portion and the top portion includes implanted dopants.

3. The transistor as recited in claim 1 , wherein the fins include side wall spacers and the fin is recessed below spacers wherein a portion of the raised source and drain regions is formed between the spacers of each fin and in contact with the fin recessed below the spacers.

4. The transistor as recited in claim 1 , further comprising a mixed metal layer formed over the raised source and drain regions.

5. The transistor as recited in claim 1 , wherein the III-V material of the plurality of parallel fins is selected from the group consisting of AlInGaAs, AlGaAs, InGaP, InAs, GaN, GaSb, InSb, InGaAs, InP, GaAs, GaP and combinations thereof.

6. The transistor as recited in claim 1 , wherein a composition of the dielectric layer is selected from the group consisting of silicon oxide, aluminum oxide, silicon nitride, silicon oxynitride and a combination thereof.

7. The transistor as recited in claim 1 , wherein a composition of the gate dielectric is selected from the group consisting of silicon oxide, silicon oxynitride, hafnium oxide and combinations thereof.

8. The transistor as recited in claim 1 , wherein a composition of the gate conductor is selected from the group consisting of copper, aluminum, tungsten, titanium nitride and a combination thereof.

9. The transistor as recited in claim 1 , wherein the III-V material of the raised source and drain regions is selected from the group consisting of AlInGaAs, AlGaAs, InGaP, InAs, GaN, GaSb, InSb, InGaAs, InP, GaAs, GaP and combinations thereof.

10. The transistor as recited in claim 1 further comprising a guard ring present around an edge of the transistor.

Assignees

• IBM

Inventors

• Basu Anirban
• Cheng Cheng-Wei
• Majumdar Amlan
• Martin Ryan M
• Rana Uzma
• Sadana Devendra K
• Shiu Kuen-Ting
• Sun Yanning

Classifications

• H10D30/024 Primary

  of fin field-effect transistors [FinFET] · CPC title

• H10D30/62 Primary

  Fin field-effect transistors [FinFET] · CPC title

• H01L29/785 Primary

  Electricity · mapped topic