Package structures and methods of forming

Patent metadata

Field	Value
Publication number	US-10177115-B2
Application number	US-201414478471-A
Country	US
Kind code	B2
Filing date	Sep 5, 2014
Priority date	Sep 5, 2014
Publication date	Jan 8, 2019
Grant date	Jan 8, 2019

Abstract

Methods of forming and structures of packages are discussed herein. In an embodiment, a method includes forming a back side redistribution structure, and after forming the back side redistribution structure, adhering a first integrated circuit die to the back side redistribution structure. The method further includes encapsulating the first integrated circuit die on the back side redistribution structure with an encapsulant, forming a front side redistribution structure on the encapsulant, and electrically coupling a second integrated circuit die to the first integrated circuit die. The second integrated circuit die is electrically coupled to the first integrated circuit die through first external electrical connectors mechanically attached to the front side redistribution structure.

First claim

What is claimed is:

1. A method comprising:
forming a back side redistribution structure over a carrier substrate, forming the back side redistribution structure comprising:
forming a first insulating layer over the carrier substrate;
forming a first metal feature over the first insulating layer;
forming a second insulating layer over the first insulating layer and the first metal feature; and
forming one or more additional second metal features and one or more third insulating layers, adjacent ones of the one or more additional second metal features being separated by corresponding ones of the one or more third insulating layers, the one or more additional second metal features comprising an uppermost metal feature and the one or more third insulating layers comprising an uppermost insulating layer over the uppermost metal feature;

after forming the back side redistribution structure, adhering a first integrated circuit die to the back side redistribution structure, the adhering comprising applying an adhesive to a bottom surface of the first integrated circuit die and using a pick-and-place tool to place the first integrated circuit die on a topmost dielectric layer of the back side redistribution structure, the bottom surface of the first integrated circuit die being separated from the uppermost insulating layer of the back side redistribution structure by the adhesive;
after forming the back side redistribution structure, forming a through via on the back side redistribution structure, the through via extending through the uppermost insulating layer to the uppermost metal feature;
after forming the back side redistribution structure, encapsulating the first integrated circuit die on the back side redistribution structure with an encapsulant;
after forming the back side redistribution structure, forming a front side redistribution structure on the encapsulant;
electrically coupling a second integrated circuit die to the first integrated circuit die, the second integrated circuit die being electrically coupled to the first integrated circuit die through first external electrical connectors mechanically attached to the front side redistribution structure;
removing the carrier substrate;
forming an opening in the first insulating layer to expose the first metal feature; and
forming a solder feature, the solder feature extending through the first insulating layer to the first metal feature.

2. The method of claim 1 , wherein after the forming the front side redistribution structure, an active side of the first integrated circuit die faces the front side redistribution structure.

3. The method of claim 1 , wherein forming through via comprises forming a seed layer on the back side redistribution structure, forming a photo resist on the seed layer, forming openings in the photo resist, forming a conductive material in the openings, removing the photo resist, and removing exposed portions of the seed layer, wherein after the encapsulating, the through via extend through the encapsulant.

4. The method of claim 1 further comprising forming an epoxy flux around the solder feature.

5. The method of claim 1 , wherein the second integrated circuit die is in a package, the package being mechanically attached to the front side redistribution structure by the first external electrical connectors.

6. The method of claim 1 , wherein the front side redistribution structure comprises an uppermost front side insulating layer, and wherein the first external electrical connectors comprises an underbump metallization extending through the uppermost front side insulating layer and a solder joint on the underbump metallization.

7. The method of claim 1 , further comprising, after forming the back side redistribution structure and prior to forming the front side redistribution structure, adhering a third integrated circuit die to the back side redistribution structure, wherein the second integrated circuit die laterally overlaps the first integrated circuit die and the third integrated circuit die.

8. A method comprising:
forming a first redistribution structure over a carrier substrate, forming the first redistribution structure comprising:
forming a first insulating layer over the carrier substrate; and
forming metallization layers over the first insulating layer, each of the metallization layers being covered by one or more insulating layers;

after forming the first redistribution structure, forming through vias on the first redistribution structure, the forming the through vias comprising plating a conductive material on portions of the first redistribution structure;
after forming the first redistribution structure, adhering a back side of a first integrated circuit die to the first redistribution structure, a front side of the first integrated circuit die comprising a first pad and a first die connector electrically connected to the first pad, a top surface of the through vias being higher than a top surface of the first die connector;
after forming the first redistribution structure, adhering a back side of a second integrated circuit die to the first redistribution structure, a front side of the second integrated circuit die comprising a second pad and a second die connector electrically connected to the second pad, a top surface of the through vias being higher than a top surface of the second die connector;
after the adhering the back side of the first integrated circuit die and the adhering the back side of the second integrated circuit die, encapsulating the through vias, the first pad, the first die connector, and the first integrated circuit die on the first redistribution structure with an encapsulant;
grinding the encapsulant and the through vias, wherein after the grinding the top surface of the through vias, a top surface of the encapsulant, and the top surface of the first die connector are co-planar;
forming a second redistribution structure on the encapsulant, an active side of the first integrated circuit die facing the second redistribution structure, an active side of the second integrated circuit die facing the second redistribution structure;
attaching a packaged integrated circuit die to the second redistribution structure using first external electrical connectors mechanically attached to the second redistribution structure, an active side of the packaged integrated circuit die facing away from the second redistribution structure, wherein the packaged integrated circuit die extends completely over the first integrated circuit die and the second integrated circuit die; and
after attaching the packaged integrated circuit die, removing the carrier substrate.

9. The method of claim 8 further comprising forming second external electrical connectors on the first redistribution structure.

10. The method of claim 9 , wherein the forming the second external electrical connectors is performed after the attaching the packaged integrated circuit die to the second redistribution structure.

11. The method of claim 9 further comprising, after forming the second external electrical connectors, forming an epoxy flux around the second external electrical connectors.

12. The method of claim 11 , further comprising:
forming an underbump metallizations extending through a dielectric layer of the second redistribution structure, wherein the first external electrical connectors comprise solder on the underbump metallizations.

13. The method of claim 12 , further comprising, after removing the carrier substrate:
forming a backside film on the first insulating layer;
forming an opening extending through the backside film and the first insulating lay

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Yu Chen-Hua
• Yeh Der-Chyang
• Chen Hsien-Wei

Classifications

• H10P72/7436

  used to support a device or a wafer when forming electrical connections thereto · CPC title

• H10P72/744

  Details of chemical or physical process used for separating the auxiliary support from a device or a wafer · CPC title

• H10P72/743

  used as a support during manufacture of interconnect decals or build up layers · CPC title

• H10P72/7402

  Wafer tapes, e.g. grinding or dicing support tapes · CPC title

• H10P72/74

  using temporarily an auxiliary support · CPC title