Methods and apparatus for controlling substrate uniformity

Patent metadata

Field	Value
Publication number	US-10177050-B2
Application number	US-201615212938-A
Country	US
Kind code	B2
Filing date	Jul 18, 2016
Priority date	Apr 26, 2012
Publication date	Jan 8, 2019
Grant date	Jan 8, 2019

Abstract

A dynamically tunable process kit, a processing chamber having a dynamically tunable process kit, and a method for processing a substrate using a dynamically tunable process kit are provided. The dynamically tunable process kit allows one or both of the electrical and thermal state of the process kit to be changed without changing the physical construction of the process kit, thereby allowing plasma properties, and hence processing results, to be easily changed without replacing the process kit. The processing chamber having a dynamically tunable process kit includes a chamber body that includes a portion of a conductive side wall configured to be electrically controlled, and a process kit. The processing chamber includes a first control system operable to control one or both of an electrical and thermal state of the process kit and a second control system operable to control an electrical state of the portion of the side wall.

First claim

What is claimed is:

1. A method for processing a substrate in a processing chamber comprising:
transferring a substrate into the processing chamber having a process kit disposed on a substrate support assembly, the process kit comprising:
a top ring; and
a base ring adapted to concentrically support the top ring, the top and base rings having an inside diameter selected to circumscribe a semiconductor wafer;
a conductive layer coupled to a bottom surface of the base ring; and
a connector coupled to the conductive layer, wherein the connector is disposed below and in direct contact with a bottom of the conductive layer interfacing with the connector, and wherein the connector includes a tuning circuit configured to couple to the conductive layer for external and independent control of a thermal state and an electrical state of the base ring through the conductive layer;

setting one or both of electrical and thermal states of the process kit;
forming a plasma within the processing chamber; and
processing the substrate in the presence of the plasma.

2. The method of claim 1 further comprising:
setting an electrical state of a first portion of a side wall of the processing chamber independently from remaining portions of the side wall.

3. The method of claim 2 , wherein setting the electrical state of the process kit or side wall of the processing chamber comprises tuning an electrical bias applied to the process kit or the conductive side wall.

4. The method of claim 3 , wherein tuning the electrical bias comprises varying processing parameters comprising: a capacitance, an inductance and a resistance of the electrical bias.

5. The method of claim 1 , wherein setting one or both of electrical and thermal states further comprises:
supplying thermal energy to the process kit from a heating element coupled to the connector.

6. The method of claim 5 , wherein the heating element is embedded in the base ring.

7. The method of claim 1 , wherein the base ring further comprises a temperature control feature configured to enable the thermal state of the process kit to be controlled.

8. The method of claim 1 , further comprising an insulating material disposed on an inside diameter of at least one of the base ring and the top ring.

9. The method of claim 1 , wherein the top ring is fabricated from or coated with a material selected from the group consisting of silicon, silicon carbide and quartz.

10. A method for processing a substrate in a processing chamber comprising:
setting one or both of electrical and thermal states of a process kit configured to circumscribe a substrate support disposed in a processing chamber, wherein the process kit further comprises:

the process kit comprising:
a top ring; and
a base ring adapted to concentrically support the top ring, the top and base rings having an inside diameter selected to circumscribe a semiconductor wafer, the base ring having a connector configured to couple a signal to the base ring for external control of one or both of a thermal state and an electrical state of the base ring; and
setting an electrical state of a first portion of a side wall of the processing chamber independently from remaining portions of the side wall.

11. The method of claim 10 , wherein setting the electrical state of the process kit or side wall of the processing chamber comprises tuning an electrical bias applied to the process kit or the conductive side wall.

12. The method of claim 11 , wherein tuning the electrical bias comprises varying processing parameters comprising: a capacitance, an inductance and a resistance of the electrical bias.

Assignees

• Applied Materials Inc

Inventors

• Sadjadi S M Reza
• Lubomirsky Dmitry
• Noorbakhsh Hamid
• Ye John Zheng
• Quach David H
• Kang Sean S

Classifications

• H10P72/7611

  characterised by edge profile or support profile · CPC title

• H10P72/722

  Details of electrostatic chucks · CPC title

• H10P72/0602

  Temperature monitoring · CPC title

• H10P72/0434 Primary

  mainly by convection · CPC title

• H10P72/0421

  for drying etching · CPC title