Non-volatile memory device having dummy cells and memory system including the same

Patent metadata

Field	Value
Publication number	US-10163475-B2
Application number	US-201715647658-A
Country	US
Kind code	B2
Filing date	Jul 12, 2017
Priority date	Dec 14, 2016
Publication date	Dec 25, 2018
Grant date	Dec 25, 2018

Abstract

A non-volatile memory device includes a cell string, a ground select transistor, and at least one dummy cell. The cell string includes at least one memory cell. The at least one dummy cell is provided between the at least one memory cell and the ground select transistor and is connected to a bit line. A controller executes dummy cell control logic configured to control a gate voltage of the at least one dummy cell to be lower than a threshold voltage of the at least one dummy cell in at least a part of a pre-charge period.

First claim

What is claimed is:

1. A non-volatile memory device, comprising:
a cell string comprising at least one memory cell, a ground select transistor, and at least one dummy cell between the at least one memory cell and the ground select transistor and connected to a bit line; and
a controller that executes dummy cell control logic configured to control a gate voltage of the at least one dummy cell to be lower than a threshold voltage of the at least one dummy cell in at least a part of a pre-charge period,
wherein the dummy cell control logic controls the gate voltage of the at least one dummy cell to switch between a turn on voltage and a turn off voltage of the at least one dummy cell at least once in the pre-charge period.

2. The non-volatile memory device according to claim 1 , further comprising:
a page buffer connected to the bit line,
wherein the page buffer applies a pre-charge voltage to the bit line in the pre-charge period.

3. The non-volatile memory device according to claim 1 ,
wherein the dummy cell control logic controls the gate voltage of the at least one dummy cell to be lower than the threshold voltage of the at least one dummy cell before a start of the pre-charge period.

4. The non-volatile memory device according to claim 1 ,
wherein the dummy cell control logic controls the gate voltage of the at least one dummy cell to be higher than the threshold voltage of the at least one dummy cell after an end of the pre-charge period.

5. The non-volatile memory device according to claim 1 ,
wherein select transistor control logic is configured, when executed, to control a gate voltage of the ground select transistor to be higher than a threshold voltage of the ground select transistor in the pre-charge period.

6. The non-volatile memory device according to claim 1 ,
wherein select transistor control logic is configured, when executed, to control a gate voltage of the ground select transistor to be lower than a threshold voltage of the ground select transistor in at least a part of the pre-charge period.

7. The non-volatile memory device according to claim 6 ,
wherein the select transistor control logic controls the gate voltage of the ground select transistor to be higher than the threshold voltage of the ground select transistor before an end of the pre-charge period.

8. The non-volatile memory device according to claim 1 ,
wherein the dummy cell control logic controls the gate voltage of the at least one dummy cell in order to set the threshold voltage of the at least one dummy cell.

9. The non-volatile memory device according to claim 1 , further comprising:
a substrate,
wherein the at least one memory cell, the at least one dummy cell, and the ground select transistor are respectively connected to at least one word line, at least one dummy word line, and at least one ground select line that are vertically stacked on the substrate.

10. The non-volatile memory device according to claim 1 ,
wherein the cell string is a NAND cell string.

11. A non-volatile memory device, comprising:
a memory cell array comprising a plurality of cell strings each comprising at least one dummy cell;
a page buffer connected to the memory cell array through a plurality of bit lines and pre-charging at least one of the plurality of bit lines; and
a controller that executes dummy cell control logic configured to control a gate voltage of the at least one dummy cell and to control a turn off voltage of the at least one dummy cell to be applied to a gate of the at least one dummy cell in at least a part of a pre-charge period in which the page buffer pre-charges at least one of the plurality of bit lines,
wherein the dummy cell control logic controls a gate voltage of at least one dummy cell to switch between a turn on voltage and a turn off voltage of each of the at least one dummy cell at least once in the pre-charge period in which the page buffer pre-charges the at least one of the plurality of bit lines.

12. The non-volatile memory device according to claim 11 ,
wherein each of the plurality of cell strings further comprises at least one memory cell and at least one ground select transistor, and
wherein the at least one dummy cell is disposed between the at least one memory cell and the at least one ground select transistor.

13. The non-volatile memory device according to claim 12 ,
wherein select transistor control logic is configured, when executed, to control a gate voltage of the at least one ground select transistor, and
wherein the select transistor control logic controls a turn on voltage of the at least one ground select transistor to be applied to a gate of the at least one ground select transistor in the pre-charge period in which the page buffer pre-charges the at least one of the plurality of bit lines.

14. A method for controlling a non-volatile memory device, comprising:
setting a threshold voltage of at least one dummy cell in a cell string of the non-volatile memory device;
controlling, by a controller in the non-volatile memory device, a gate voltage of the at least one dummy cell to be lower than the threshold voltage of the at least one dummy cell in at least a part of a pre-charge period by executing dummy cell control logic, and
controlling, by the controller, a gate voltage of at least one dummy cell to switch between a turn on voltage and a turn off voltage of each of the at least one dummy cell at least once in the pre-charge period,
wherein the at least one dummy cell is between at least one memory cell and a ground select transistor in the cell string, and
wherein the at least one dummy cell is connected to a bit line.

15. The method for controlling a non-volatile memory device according to claim 14 , further comprising:
applying, by a page buffer connected to the bit line, a pre-charge voltage to the bit line in the pre-charge period to isolate the cell string from a common source line.

16. The method for controlling a non-volatile memory device according to claim 14 ,
wherein the dummy cell control logic controls the gate voltage of the at least one dummy cell to be lower than the threshold voltage of the at least one dummy cell before a start of the pre-charge period, and
wherein the dummy cell control logic controls the gate voltage of the at least one dummy cell to be higher than the threshold voltage of the at least one dummy cell after an end of the pre-charge period so that a read operation can be performed.

17. The method for controlling a non-volatile memory device according to claim 14 ,
wherein the dummy cell control logic controls the gate voltage of the at least one dummy cell in order to set the threshold voltage of the at least one dummy cell.

18. The method for controlling a non-volatile memory device according to claim 14 ,
wherein the cell string is a NAND cell string, and
wherein the non-volatile memory device comprises a memory cell array that includes the cell string and a page buffer connected to the memory cell array through a plurality of bit lines and pre-charging at least one of the plurality of bit lines.

Assignees

• Samsung Electronics Co Ltd

Inventors

• Yu Chang-Yeon
• Park June-Hong
• Kim Seong-Jin

Classifications

• G11C7/227 Primary

  Timing of memory operations based on dummy memory elements or replica circuits · CPC title

• G11C7/22

  Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management · CPC title

• G11C7/225

  Clock input buffers · CPC title

• G11C7/18

  Bit line organisation; Bit line lay-out · CPC title

• G11C16/0483

  comprising cells having several storage transistors connected in series · CPC title