Memory devices and methods of operating the memory devices by programming normal cells after programming a first dummy cell

Patent metadata

Field	Value
Publication number	US-9721664-B2
Application number	US-201514605433-A
Country	US
Kind code	B2
Filing date	Jan 26, 2015
Priority date	Apr 14, 2014
Publication date	Aug 1, 2017
Grant date	Aug 1, 2017

Abstract

A method of operating a memory device including a first memory block having a plurality cell strings is provided. Each of the plurality of cell strings includes a string selection transistor connected in series to a first dummy cell, a plurality of normal cells, a second dummy cell and a ground selection transistor. The method includes programming the first dummy cell, and programming the normal cells in at least one of the cell strings after the programming the first dummy cell. The normal cells are selected based on a first program command inputted to the memory device. The programming the first dummy cell is performed at least twice before the normal cells are programmed. A number of times of programming the first dummy cell is different according to a level of a voltage applied to the first dummy cell and a level of a voltage applied to the normal cells.

First claim

What is claimed is:

1. A method of operating a memory device including a first memory block having a plurality of cell strings, each of the plurality of cell strings including a string selection transistor connected in series to a first dummy cell, a plurality of normal cells, a second dummy cell and a ground selection transistor, the method comprising:
programming the first dummy cell; and
programming the normal cells in at least one of the plurality of cell strings after the programming the first dummy cell, the normal cells being selected based on a first program command inputted to the memory device, wherein
the programming the first dummy cell is performed at least twice before the normal cells are programmed, and
a number of times of programming the first dummy cell is different according to a level of a voltage applied to the first dummy cell and a level of a voltage applied to the plurality of normal cells.

2. The method of claim 1 , wherein the programming the first dummy cell is performed in response to the first program command or the programming the first dummy cell is performed after performing an erasure operation on the first memory block regardless of the first program command being inputted to the memory device.

3. The method of claim 1 , wherein the programming the first dummy cell includes:
programming the first dummy cell;
applying a ground voltage to the string selection transistor and the ground selection transistor;
applying a first pass voltage to the first and second dummy cells; and
applying a second pass voltage to the plurality of normal cells.

4. The method of claim 1 , wherein the programming the first dummy cell includes:
applying a first voltage to the string selection transistor;
applying a ground voltage to the ground selection transistor;
applying a program voltage to the first dummy cell; and
applying a pass voltage to the second dummy cell and the plurality of normal cells.

5. The method of claim 4 , wherein
each of the plurality of cell strings further includes a third dummy cell between the string selection transistor and the first dummy cell,
each of the plurality of cell strings further includes a fourth dummy cell between the ground selection transistor and the second dummy cell; and
the programming the first dummy cell further includes applying a voltage lower than the pass voltage to the third and fourth dummy cells.

6. The method of claim 1 , wherein the programming the first dummy cell is selectively performed on at least one cell string if a threshold voltage of the string selection transistor or the ground selection transistor in the at least one cell string is lower than a first reference voltage.

7. The method of claim 1 , further comprising:
erasing the first memory block after the normal cells are programmed; and
reprogramming the first dummy cell, wherein the reprogramming of the first dummy cell is performed using a voltage different from a program voltage which is applied to the first dummy cell in programming the first dummy cell.

8. The method of claim 7 , further comprising:
programming the normal cells in at least one cell string selected by a second program command additionally inputted to the memory device after the first dummy cells are reprogrammed,
wherein the programming of the normal cells in the at least one cell string selected by the second program command is performed using a voltage different from a voltage that is used in the programming the normal cells of the at least one cell string selected by the first program command.

9. The method of claim 1 , wherein the memory device includes a memory cell array, a controller, and a driver,
the memory cell array includes the first memory block,
the programming the first dummy cell includes increasing a threshold voltage of at least one dummy cell in at least one of the plurality of cell strings in the first memory block, and
the programming the normal cells includes programming the normal cells in a selected string among the plurality of cell strings after the increasing the threshold voltage of the at least one dummy cell.

10. The method of claim 9 , wherein
the increasing the threshold voltage of the at least one dummy cell includes using one of a hot carrier injection (HCI) mechanism and a Fowler-Nordheim (F-N) tunneling mechanism to program the at least one dummy cell before the programming the plurality of normal cells, and
the at least one dummy cell includes the first dummy cell and the second dummy cell in the at least one of the plurality of cell strings.

11. The method of claim 10 , wherein
the HCI mechanism is used during the increasing the threshold voltage of the at least one dummy cell, and
the HCI mechanism includes,
turning the string selection transistor and the ground selection transistor off in the at least one of the plurality of cell strings,
applying a first pass voltage to the first dummy cell and the second dummy cell in the at least one of the plurality of cell strings, and
applying a second pass voltage to the plurality of normal cells in the at least one of the plurality of cell strings, wherein
the second pass voltage is greater than the first pass voltage.

12. The method of claim 11 ,
the F-N tunneling mechanism is used during the increasing the threshold voltage of the at least one dummy cell, and
the F-N tunneling mechanism includes turning the ground selection transistor off in the at least one of the plurality of cell strings,
applying a first voltage to the string selection transistor in the at least one of the plurality of cell strings,
applying a program voltage to the first dummy cell in the at least one of the plurality of cell strings,
applying a first pass voltage to the second dummy cell in the at least one of the plurality of cell strings, and
applying a second pass voltage to the plurality of normal cells in the at least one of the plurality of cell strings, wherein
a value of the first pass voltage is greater than a value of a ground voltage and less than a value of the program voltage,
a value of the second pass voltage is greater than the value of the ground voltage and less than the value of the program voltage, and
the first voltage is a power supply voltage.

13. The method of claim 9 , wherein,
in each of the plurality of cell strings,
the second dummy cell is on top of the ground selection transistor, the plurality of normal cells are on top of the second dummy cell, the first dummy cell is on top of the plurality of normal cells, and the string selection transistor is on top of the first dummy cell,
the programming the plurality of normal cells in the selected string is performed in response to a program command received by the controller, a control signal generated by the controller and transferred to the driver in response to the program command, and an address decoded by the driver,
the programming the plurality of normal cells in the selected string includes the driver applying an operation voltage set to the selected string in response to the control signal transferred to the driver by the controller, and
the increasing the threshold voltage of the at least one dummy cell is performed in response to the controller receiving the program command, or
the increasing the threshold voltage of the at least one dummy cell is performed after performing an erasure operation on the first memory block regardless of the controller receiving the program command.

14. The method of claim 1 , wherein an erase operation on the first memory block is not performed between the programming the first dummy cell and the pro

Assignees

• Nam Sang-Wan
• Kang Kyung-Min
• Samsung Electronics Co Ltd

Inventors

• Nam Sang-Wan
• Kang Kyung-Min

Classifications

• G11C16/10 Primary

  Programming or data input circuits · CPC title

• G11C16/0483

  comprising cells having several storage transistors connected in series · CPC title

• G11C7/14

  Dummy cell management; Sense reference voltage generators · CPC title