Semiconductor memory device and method of operating the same

Patent metadata

Field	Value
Publication number	US-9349465-B2
Application number	US-201414154839-A
Country	US
Kind code	B2
Filing date	Jan 14, 2014
Priority date	Jul 2, 2013
Publication date	May 24, 2016
Grant date	May 24, 2016

Abstract

A semiconductor memory device and a method of operating the same are provided. The semiconductor memory device includes memory cells stacked on a substrate. The method includes applying a reference voltage to an unselected drain select line, applying a drain selection voltage to a selected drain select line, and applying a word line voltage to a normal word line. Before the word line voltage is applied to the normal word line, a positive voltage is applied to a dummy word line to bounce the unselected drain select line.

First claim

What is claimed is:

1. A method of operating a semiconductor memory device comprising memory cells stacked on a substrate, the method comprising:
applying a reference voltage to an unselected drain select line;
applying a drain selection voltage to a selected drain select line; and
applying a word line voltage to a normal word line,
wherein
a precharge voltage is applied to the unselected drain select line before the reference voltage is applied to the unselected drain select line,
a positive voltage is applied to a dummy word line when the precharge voltage is applied to the unselected drain select line,
the positive voltage is applied to the dummy word line before the word line voltage is applied to the normal word line, and
the positive voltage applied to the dummy word line is maintained until the application of the word line voltage is ended.

2. The method of claim 1 , wherein the positive voltage applied to the dummy word line bounces the unselected drain select line.

3. The method of claim 1 , wherein the positive voltage is applied to the dummy word line during the application of the reference voltage to the unselected drain select line.

4. The method of claim 1 , wherein the application of the precharge voltage is ended before the word line voltage is applied to the normal word line.

5. The method of claim 1 , wherein, during the application of the drain selection voltage to the selected drain select line, the positive voltage is applied to the dummy word line.

6. The method of claim 1 , wherein the precharge voltage applied to the unselected drain select line is a first precharge voltage, and before the drain selection voltage is applied to the selected drain select line, the positive voltage is applied to the dummy word line during an application of a second precharge voltage to the selected drain select line.

7. The method of claim 6 , wherein the application of the second precharge voltage is ended before the word line voltage is applied to the normal word line.

8. A semiconductor memory device, comprising:
a memory cell array comprising memory cells stacked on a substrate, the memory cells connected with each other into cell strings; and
a peripheral circuit configured to
apply a reference voltage to an unselected drain select line of an unselected cell string of the cell strings,
apply a word line voltage to a normal word line of the cell strings, and
apply a positive voltage to a dummy word line of the cell strings before the word line voltage is applied to the normal word line,
apply a precharge voltage to the unselected drain select line before the reference voltage is applied to the unselected drain select line,
apply the positive voltage to the dummy word line when the precharge voltage is applied to the unselected drain select line, and
maintain the positive voltage applied to the dummy word line until the application of the word line voltage is ended.

9. The device of claim 8 , wherein the peripheral circuit is configured to apply the positive voltage to the dummy word line to bounce the unselected drain select line.

10. The device of claim 8 , wherein the peripheral circuit is configured to apply the positive voltage to the dummy word line during the application of the reference voltage to the unselected drain select line.

11. The device of claim 8 , wherein the peripheral circuit is further configured to end the application of the precharge voltage before the word line voltage is applied to the normal word line.

12. The device of claim 8 , wherein the peripheral circuit is further configured to apply the positive voltage to the dummy word line during an application of a drain selection voltage to a selected drain select line of the selected cell string.

13. The device of claim 8 , wherein the precharge voltage applied to the unselected drain select line is a first precharge voltage, and before the drain selection voltage is applied to a selected drain select line of the selected cell string, the peripheral circuit is further configured to apply the positive voltage to the dummy word line during an application of a second precharge voltage to the selected drain select line.

14. The device of claim 13 , wherein the peripheral circuit is configured to end the application of the second precharge voltage before the word line voltage is applied to the normal word line.

15. A memory system, comprising:
a semiconductor memory device; and
a controller configured to control the semiconductor memory device,
wherein the semiconductor memory device comprises:
a memory cell array including memory cells stacked on a substrate, the memory cells connected with each other into cell strings; and
a peripheral circuit configured to
apply a reference voltage to an unselected drain select line of an unselected cell string of the cell strings,
apply a word line voltage to a normal word line of the cell strings, and
apply a positive voltage to a dummy word line of the cell strings before the word line voltage is applied to the normal word line,
apply a precharge voltage to the unselected drain select line before the reference voltage is applied to the unselected drain select line,
apply the positive voltage to the dummy word line when the precharge voltage is applied to the unselected drain select line, and
maintain the positive voltage applied to the dummy word line until the application of the word line voltage is ended.

16. The system of claim 15 , wherein the peripheral circuit is further configured to apply the positive voltage to the dummy word line to bounce the unselected drain select line.

Assignees

• Sk Hynix Inc

Inventors

• Jang Yoon Soo

Classifications

• G11C16/3427

  Circuits or methods to prevent or reduce disturbance of the state of a memory cell when neighbouring cells are read or written · CPC title

• G11C16/0483

  comprising cells having several storage transistors connected in series · CPC title

• G11C16/0408

  comprising cells containing floating gate transistors (G11C16/0483, G11C16/0491 take precedence) · CPC title

• G11C16/24 Primary

  Bit-line control circuits · CPC title

• H01L27/1157

  Electricity · mapped topic