Nonvolatile memory device, erase method thereof and memory system including the same

Patent metadata

Field	Value
Publication number	US-9514828-B2
Application number	US-201514814846-A
Country	US
Kind code	B2
Filing date	Jul 31, 2015
Priority date	Nov 13, 2014
Publication date	Dec 6, 2016
Grant date	Dec 6, 2016

Abstract

An erase method of a nonvolatile memory device including a plurality of cell strings on a substrate is provided. Each string includes a plurality of memory cells stacked in a direction perpendicular to the substrate, a ground select transistor between the memory cells and the substrate, and string select transistors between the memory cells and a bit line. The erase method includes applying a precharge voltage during a first time to a first string select line, floating the first string select line during a second time after the first time, and applying an erase voltage to the substrate after the first time. The first string select line is connected to the string select transistors at a first height in the cell strings of a same row.

First claim

What is claimed is:

1. A nonvolatile memory device comprising:
a memory cell array including a plurality of cell strings on a substrate, each of the cell strings including a plurality of cell transistors stacked on top of each other in a direction perpendicular to the substrate;
an address decoder connected to the cell strings through a ground select line, word lines, dummy word lines and string select lines;
a read & write circuit connected to the cell strings through bit lines; and
a voltage generator,
the voltage generator being configured to apply a precharge voltage during a first time of an erase operation to a first string select line among the string select lines, the first string select line being adjacent to the word lines,
the voltage generator being configured to apply an erase voltage to the substrate and to apply voltages to the address decoder so that the first string select line is floated according to the erase voltage after applying the precharge voltage during the first time to the first string select line,
wherein the address decoder is configured to concurrently float the ground select line and a dummy word line adjacent to the ground select line among the dummy word lines between the ground select line and the word lines.

2. The nonvolatile memory device of claim 1 , wherein the address decoder is configured to float the first string select line when the voltage generator applies the erase voltage to the substrate.

3. The nonvolatile memory device of claim 1 , wherein
the string select lines includes a second string select line above the first string select line, and
the address decoder is configured to float the second string select line when the first string select line is floated.

4. The nonvolatile memory device of claim 1 , wherein the address decoder is configured to float the ground select line after a specific time from when the erase operation begins.

5. The nonvolatile memory device of claim 1 , wherein
some of the dummy word lines are between the first string select line and the word lines, and
the address decoder is configured to drive at least one of the dummy word lines between the first string select line and the word lines by using a word line erase voltage.

6. The nonvolatile memory device of claim 1 , wherein the memory cell array comprises a plurality of sub blocks.

7. The nonvolatile memory device of claim 6 , wherein
the address decoder is connected to the sub blocks through the word lines,
the address decoder is configured to apply a word line erase voltage to the word lines connected to a selected sub block among the plurality of sub blocks,

the address decoder is configured to apply a precharge voltage to a word line adjacent to the selected sub block and connected to an unselected sub block among the plurality of sub blocks during a time interval in the erase operation, and
the address decoder is configured to float all the word lines connected to the unselected sub block if the address decoder applies the erase voltage to the substrate.

8. The nonvolatile memory device of claim 7 , wherein the selected sub block is between the unselected sub block and the first string select line.

9. A memory system comprising:
the nonvolatile memory device of claim 1 ; and
a controller configured to control the nonvolatile memory device.

10. A nonvolatile memory device comprising:
a plurality of cell strings on a substrate, each of the cell strings including a plurality of cell transistors stacked on top of each other between a ground select transistor and a string select transistor, each of the cell strings including at least one of,
a first dummy cell transistor between the string select transistor and the cell transistors, and
a second dummy cell transistor between the ground select transistor and the cell transistors; and

a control circuit connected to the substrate and connected to the plurality of cell strings through a plurality of bit lines, a ground select line, word lines, at least one dummy word line, and a string select line,
the control circuit during a first time interval of an erase operation being configured to apply a precharge voltage to at least one of the string select line and one of the word lines,
the control circuit, during the erase operation after the first time interval, being configured to apply an erase voltage to the substrate and float the string select line according to the erase voltage applied to the substrate.

11. A nonvolatile memory device comprising:
a plurality of cell strings on a substrate, each of the cell strings including a plurality of cell transistors stacked on top of each other between a ground select transistor and a string select transistor, each of the cell strings including at least one of,
a dummy cell transistor between the string select transistor and the cell transistors, and

a dummy cell transistor between the ground select transistor and the cell transistors; and
a control circuit connected to the substrate and connected to the plurality of cell strings through a plurality of bit lines, a ground select line, word lines, at least one dummy word line, and a string select line,
the control circuit during a first time interval of an erase operation being configured to apply a precharge voltage to at least one of the string select line and one of the word lines,
the control circuit, during the erase operation after the first time interval, being configured to apply an erase voltage to the substrate and float the string select line according to the erase voltage applied to the substrate, wherein
the string select transistor in each of the cell strings is a first string select transistor,
the cell strings each include a second string select transistor on the first string select transistor,
the dummy cell transistor between the ground select transistor and the cell transistors is a first dummy cell transistor,
the cell strings each include a second dummy cell transistor between the cell transistors and the first dummy cell transistor,
the dummy cell transistor between the first string select transistor and the cell transistors is a third dummy cell transistor, and
the cell strings each include a fourth dummy cell transistor between the first string select transistor and the third dummy cell transistor.

12. The nonvolatile memory device of claim 11 , wherein
the string select line is a first string select line that connects the control circuit to the first string select transistors of the cell strings in a same row of the cell strings,
the second string select transistors in the same row of cell strings are connected to the control circuit through a second string select line,
the control circuit during the first interval of the erase operation is configured to apply a ground voltage to the second string select line,
the control circuit during the erase operation after the first time interval is configured to float the first string select line at a first voltage level and to float the second string select line at a second voltage level according to the erase voltage applied to the substrate, and
the first voltage level is less than the second voltage level.

13. The nonvolatile memory device of claim 11 , wherein
the string select line is a first string select line that connects the control circuit to the first string select transistors of the cell strings in a same row of the cell strings,
the second string select transistors in the same row of cell strings are connected to the control circuit through a second string select line,
the control circuit during the first interval of the erase operation is configured to a

Assignees

• Shim Wonbo
• Samsung Electronics Co Ltd

Inventors

• Shim Wonbo

Classifications

• G11C16/14

  Circuits for erasing electrically, e.g. erase voltage switching circuits · CPC title

• G11C16/26

  Sensing or reading circuits; Data output circuits · CPC title

• G11C16/08

  Address circuits; Decoders; Word-line control circuits · CPC title

• G11C16/30

  Power supply circuits · CPC title

• G11C16/24 Primary

  Bit-line control circuits · CPC title