Circuit for generating a sense amplifier enable signal with variable timing

Patent metadata

Field	Value
Publication number	US-9685209-B1
Application number	US-201615132388-A
Country	US
Kind code	B1
Filing date	Apr 19, 2016
Priority date	Apr 19, 2016
Publication date	Jun 20, 2017
Grant date	Jun 20, 2017

Abstract

A sense amplifier enable signal generating circuit includes an input coupled to a dummy bit line of a memory. A voltage comparator circuit compares a voltage on the dummy bit line to a threshold voltage and generates an output signal when the voltage falls below that threshold voltage. A multi-bit counter circuit counts a count value in response to the output signal. A pull-up circuit pulls up the voltage on the dummy bit line in response to the output signal. A count comparator circuit compares the count value to a count threshold and generates a sense amplifier enable signal when the count value equals the count threshold.

First claim

What is claimed is:

1. A sense amplifier enable signal generating circuit, comprising:
an input coupled to a dummy bit line of a memory;
a voltage comparator circuit configured to compare a voltage on the dummy bit line to a threshold voltage and generate an output signal in response thereto;
a multi-bit counter circuit configured to count a count value in response to the output signal;
a pull-up circuit configured to pull up the voltage on the dummy bit line in response to the output signal; and
a count comparator circuit configured to compare the count value to a count threshold and generate a sense amplifier enable signal in response thereto.

2. The circuit of claim 1 , wherein the multi-bit counter circuit is an incrementing counter and the count value is incremented in response to the output signal, and wherein the count comparator circuit generates the sense amplifier enable signal when the incremented count value reaches a threshold count value.

3. The circuit of claim 1 , wherein the multi-bit counter circuit is a decrementing counter and the count value is decremented in response to the output signal, and wherein the count comparator circuit generates the sense amplifier enable signal when the decremented count value reaches a threshold count value.

4. The circuit of claim 1 , wherein the multi-bit counter circuit is configured to reset to a starting count value in response to a precharging of the dummy bit line.

5. The circuit of claim 1 , wherein the pull-up circuit is further configured to pull up the voltage on the dummy bit line to precharge the dummy bit line in advance of a read operation on the memory.

6. The circuit of claim 1 , wherein a value of the count threshold is dependent on a supply voltage level for the memory.

7. The circuit of claim 1 , wherein a value of the count threshold is selected in response to a signal indicative of a supply voltage level for the memory.

8. A sense amplifier enable signal generating circuit, comprising:
an input coupled to a dummy bit line of a memory;
a first circuit configured to selectively pull up a voltage on the dummy bit line in response to the voltage on the dummy bit line falling below a voltage threshold;
a second circuit configured to increment or decrement a count value each time the voltage on the dummy bit line falls below the voltage threshold; and
a third circuit configured to generate a sense amplifier enable signal in response to the count value meeting a count threshold.

9. The circuit of claim 8 , wherein the second circuit increments or decrements said count value during a time period when a word line of the memory is asserted.

10. The circuit of claim 8 , wherein the first circuit repeatedly selectively pulls up during a time period when a word line of the memory is asserted.

11. The circuit of claim 8 , wherein said count value is reset to a starting count value in response to a precharging of the dummy bit line.

12. The circuit of claim 8 , wherein said first circuit is further configured to pull up the voltage on the dummy bit line to precharge the dummy bit line in advance of a read operation on the memory.

13. The circuit of claim 8 , wherein a value of the count threshold is dependent on a supply voltage level for the memory.

14. The circuit of claim 8 , wherein a value of the count threshold is selected in response to a signal indicative of a supply voltage level for the memory.

15. A method, comprising:
sensing a falling voltage on a dummy bit line of a memory in response to assertion of a word line signal;
selectively pulling up the voltage on the dummy bit line in response to the voltage falling below a voltage threshold;
counting, during a time period when a word line of the memory is asserted, a number of times the voltage on the dummy bit line falls below the voltage threshold; and
generating a sense amplifier enable signal in response to the counted number of times meeting a count threshold.

16. The method of claim 15 , further comprising resetting the count to a starting count value in response to a precharging of the dummy bit line.

17. The method of claim 15 , further comprising pulling up the voltage on the dummy bit line to precharge the dummy bit line in advance of a read operation on the memory.

18. The method of claim 15 , wherein a value of the second threshold is dependent on a supply voltage level for the memory.

19. The method of claim 15 , wherein a value of the second threshold is selected in response to a signal indicative of a supply voltage level for the memory.

20. A sense amplifier enable signal generating circuit, comprising:
an input coupled to a dummy bit line of a memory;
a first circuit configured to selectively pull up a voltage on the dummy bit line in response to the voltage on the dummy bit line falling below a first threshold;
a second circuit configured to count, during a time period when a word line of the memory is asserted, a number of times the voltage on the dummy bit line falls below the first threshold; and
a third circuit configured to generate a sense amplifier enable signal in response to the counted number of times meeting a second threshold.

21. The circuit of claim 20 , wherein the first circuit repeatedly selectively pulls up during a time period when the word line of the memory is asserted.

22. The circuit of claim 20 , wherein said count is reset to a starting count value in response to a precharging of the dummy bit line.

23. The circuit of claim 20 , wherein said first circuit is further configured to pull up the voltage on the dummy bit line to precharge the dummy bit line in advance of a read operation on the memory.

24. The circuit of claim 20 , wherein a value of the second threshold is dependent on a supply voltage level for the memory.

25. The circuit of claim 20 , wherein a value of the second threshold is selected in response to a signal indicative of a supply voltage level for the memory.

26. A method, comprising:
resetting a count to a starting count value in response to a precharging of a dummy bit line of a memory;
sensing a falling voltage on the dummy bit line in response to assertion of a word line signal;
selectively pulling up the voltage on the dummy bit line in response to the voltage falling below a first threshold;
counting a number of times the voltage on the dummy bit line falls below the first threshold; and
generating a sense amplifier enable signal in response to the counted number of times meeting a second threshold.

27. The method of claim 26 , further comprising pulling up the voltage on the dummy bit line to precharge the dummy bit line in advance of a read operation on the memory.

28. The method of claim 26 , wherein a value of the second threshold is dependent on a supply voltage level for the memory.

29. The method of claim 26 , wherein a value of the second threshold is selected in response to a signal indicative of a supply voltage level for the memory.

Assignees

• St Microelectronics Int Nv

Inventors

• Dhori Kedar Janardan
• Kumar Vinay
• Kumar Ashish

Classifications

• G11C7/14

  Dummy cell management; Sense reference voltage generators · CPC title

• G11C7/062

  Differential amplifiers of non-latching type, e.g. comparators, long-tailed pairs · CPC title

• G11C7/12 Primary

  Bit line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, equalising circuits, for bit lines · CPC title

• G11C11/413

  Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction · CPC title

• G11C7/08 Primary

  Control thereof · CPC title