Methods for processing a semiconductor workpiece

Patent metadata

Field	Value
Publication number	US-10157765-B2
Application number	US-201615359620-A
Country	US
Kind code	B2
Filing date	Nov 23, 2016
Priority date	Nov 25, 2013
Publication date	Dec 18, 2018
Grant date	Dec 18, 2018

Abstract

Methods for processing a semiconductor workpiece can include providing a semiconductor workpiece that includes one or more kerf regions; forming one or more trenches in the workpiece by removing material from the one or more kerf regions from a first side of the workpiece; mounting the workpiece with the first side to a carrier; thinning the workpiece from a second side of the workpiece; and forming a metallization layer over the second side of the workpiece.

First claim

What is claimed is:

1. A method for processing a semiconductor workpiece, the method comprising:
providing a semiconductor workpiece having one or more kerf regions;
forming a first mask layer over a first side of the workpiece, wherein the first mask layer comprises hard mask material;
patterning the first mask layer to expose the one or more kerf regions;
mounting the workpiece with the patterned first mask layer to a carrier;
forming a second mask layer over a second side of the workpiece;
patterning the second mask layer to expose the one or more kerf regions;
etching the one or more kerf regions from the second side of the workpiece to form one or more trenches in the workpiece extending from the second side to the first side of the workpiece, the one or more trenches defining a plurality of sidewalls of the workpiece extending from the first side to the second side of the workpiece;
forming a metallization layer on the second side of the workpiece and on at least one sidewall of the workpiece formed by one or more trenches after etching the one or more kerf regions, wherein the metallization layer extends on the at least one sidewall from the first side to the second side of the workpiece; and
removing the patterned first mask layer from the workpiece.

2. The method of claim 1 , wherein etching the one or more kerf regions from the second side of the workpiece comprises plasma etching the one or more kerf regions from the second side of the workpiece.

3. The method of claim 1 , further comprising thinning the workpiece from the second side after mounting the workpiece and before etching the one or more kerf regions.

4. The method of claim 3 , wherein thinning the workpiece comprises grinding the workpiece.

5. The method of claim 1 , wherein forming the metallization layer comprises sputter depositing the metallization layer.

6. The method of claim 1 , further comprising demounting the carrier from the workpiece after forming the metallization layer.

7. The method of claim 6 , further comprising laminating the workpiece with the metallization layer onto a tape before demounting the carrier from the workpiece.

8. The method of claim 1 , wherein the second side of the workpiece is opposite the first side of the workpiece.

9. The method of claim 1 , wherein the semiconductor workpiece comprises a wafer.

10. The method of claim 1 , wherein the first side is a front side of the wafer and the second side is a back side of the wafer.

11. The method of claim 1 , wherein the second mask layer includes a hard mask material.

12. The method of claim 1 , wherein the second mask layer comprises an oxide layer.

13. The method of claim 1 , wherein the first mask layer comprises an oxide layer.

14. The method of claim 1 , wherein the first mask layer is removed after forming the metallization layer.

15. The method of claim 1 , wherein the carrier is a rigid carrier.

16. A method for processing a semiconductor workpiece, the method comprising:
providing a semiconductor workpiece having one or more kerf regions;
forming a first mask layer over a first side of the workpiece;
patterning the first mask layer to expose the one or more kerf regions;
mounting the workpiece with the patterned first mask layer to a carrier, comprising applying an adhesive to bond the workpiece to the carrier, the adhesive comprising different material than the first mask layer;
forming a second mask layer over a second side of the workpiece;
patterning the second mask layer to expose the one or more kerf regions;
etching the one or more kerf regions from the second side of the workpiece to form one or more trenches in the workpiece extending from the second side to the first side of the workpiece, the one or more trenches defining a plurality of sidewalls of the workpiece that extend from the first side to the second side of the workpiece;
forming a metallization layer on the second side of the workpiece and on at least one sidewall of the workpiece formed by the one or more trenches after etching the one or more kerf regions, wherein the metallization layer extends on the at least one sidewall from the first side to the second side of the workpiece; and
removing the patterned first mask layer from the workpiece.

17. The method of claim 16 , wherein the adhesive is a continuous adhesive layer.

Assignees

• Infineon Technologies Ag

Inventors

• Stranzl Gudrun
• Zgaga Martin
• Leuschner Rainer
• Goller Bernhard
• Boche Bernhard
• Engelhardt Manfred
• Wendt Hermann
• Noehammer Bernd
• Mayer Karl
• Roesner Michael
• Voerckel Monika Cornelia

Classifications

• H10P72/7448

  the bond interface between the auxiliary support and the wafer comprising two or more, e.g. multilayer adhesive or adhesive and release layer · CPC title

• H10P72/7422

  used to protect an active side of a device or wafer · CPC title

• H10P72/7416

  used during dicing or grinding · CPC title

• H10P72/743

  used as a support during manufacture of interconnect decals or build up layers · CPC title

• H10P76/403

  for lift-off processes · CPC title