Shrink process aware assist features

Patent metadata

Field	Value
Publication number	US-10153162-B2
Application number	US-201615284773-A
Country	US
Kind code	B2
Filing date	Oct 4, 2016
Priority date	Oct 4, 2016
Publication date	Dec 11, 2018
Grant date	Dec 11, 2018

Abstract

Methods for fabricating integrated circuits are provided. In one example, a method includes providing a circuit structure layer over a substrate and at least one etch layer over the circuit structure layer, in the at least one etch layer patterning at least one primary pattern feature having at least one primary pattern feature dimension and at least one assist pattern feature having at least one assist pattern feature dimension, where the primary pattern feature dimension is greater than the assist pattern feature dimension, reducing the at least one primary pattern feature dimension and closing the assist pattern feature to form an etch pattern, and etching a circuit structure feature using the etch pattern.

First claim

What is claimed is:

1. A method of fabricating a circuit structure feature, the fabricating comprising:
providing a circuit structure layer over a substrate and a plurality of etch layers over the circuit structure layer;
forming a pattern in at least one of the plurality of etch layers wherein forming comprises patterning at least one primary pattern feature having at least one primary pattern feature dimension and a plurality of assist pattern features having at least one assist pattern feature dimension, where the primary pattern feature dimension is greater than the assist pattern feature dimension and at least one of the plurality of assist pattern features is formed in one etch layer of the plurality of etch layers without being formed in other layers of the plurality of etch layers;
reducing the at least one primary pattern feature dimension and closing at least one assist pattern feature to form an etch pattern; and
etching the circuit structure feature using the etch pattern,
wherein the plurality of assist features are arranged asymmetrically with respect to each other.

2. The method of claim 1 , wherein at least one etch layer of the plurality of etch layers comprises a photo-resist layer, and wherein the other layers of the plurality of etch layers comprise an anti-reflective coating layer disposed below the photo-resist layer and an organic planar layer disposed below the anti-reflective coating layer.

3. The method of claim 1 , wherein at least one etch layer of the plurality of etch layers comprises a hard mask layer, and wherein the other layers of the plurality of etch layers comprise an anti-reflective coating layer disposed below the photo-resist layer and an organic planar layer disposed below the anti-reflective coating layer.

4. The method of claim 1 , further comprising increasing the at least one dimension of the primary pattern feature after reducing the at least one dimension of the primary pattern feature.

5. The method of claim 1 , wherein the at least one dimension of the primary pattern feature comprises a length of the primary pattern feature.

6. The method of claim 1 , wherein the at least one dimension of the primary pattern feature comprises a width of the primary pattern feature.

7. The method of claim 1 , wherein the plurality of assist feature dimensions are smaller than the at least one primary feature dimension.

8. The method of claim 1 , wherein at least one of the plurality of the assist features comprises at least one polygon-shaped hole formed in the at least one etch layer.

9. The method of claim 1 , wherein the plurality of assist features further facilitate forming the primary pattern feature.

10. The method of claim 1 , wherein the asymmetrically arranged plurality of assist features have a variable spacing between one assist feature and one or more adjacent assist features.

11. The method of claim 9 , wherein the plurality of assist features comprise a plurality of polygon-shaped holes.

12. A method of fabricating a circuit structure feature, the fabricating comprising:
providing a circuit structure layer over a substrate and at least one etch layer over the circuit structure layer;
forming a pattern in the at least one etch layer wherein forming comprises patterning at least one primary pattern feature having at least one primary pattern feature dimension and at least one assist pattern feature having at least one assist pattern feature dimension, where the primary pattern feature dimension is greater than the assist pattern feature dimension, wherein the patterning the at least one etch layer is performed after determining if the at least one assist feature may be completely closed by the reducing the at least one dimension of the primary pattern feature;
reducing the at least one primary pattern feature dimension and closing the assist pattern feature to form an etch pattern; and
etching the circuit structure feature using the etch pattern,
wherein the primary pattern feature comprises a trench formed in the at least one etch layer, and wherein reducing the at least one dimension of the primary pattern feature comprises depositing a material over the at least one etch layer, the material at least partially filling the trench to reduce the at least one dimension of the primary pattern feature.

13. The method of claim 12 , wherein the material comprises a hard mask layer.

14. The method of claim 12 , wherein the at least one assist feature comprises a polygon-shaped assist feature, and wherein the determining comprises applying an inward bias to the polygon shape of the assist feature, the inward bias corresponding to the reducing, to detect whether the polygon shape deforms as a result of applying the inward bias, the deformation corresponding to complete closure of the at least one assist feature.

15. The method of claim 14 , wherein the polygon shape does not deform as a result of applying the inward bias, and further comprising altering one or more dimensions of the at least one assist feature so that the at least one assist feature will be completely closed by the reducing.

16. The method of claim 12 , wherein the at least one assist feature comprises a shape defined by a closed contour, and wherein the determining comprises providing a measurement circle, the measurement circle having a radius corresponding to the reducing, and comparing the measurement circle to the closed contour of the at least one assist feature to detect if the circle is larger than the closed contour.

17. The method of claim 16 , wherein the measurement circle is smaller than the closed contour, the measurement circle being smaller than the closed contour corresponding to incomplete closure of the at least one assist feature, and further comprising altering one or more dimensions of the at least one assist feature so that the at least one assist feature will be completely closed by the reducing.

Assignees

• Globalfoundries Inc

Inventors

• Kim Ryan Ryoung-Han
• Wang Wenhui
• Latypov Azat
• Coskun Jr Tamer
• Sun Lei

Classifications

• H10P74/203

  Structural properties, e.g. testing or measuring thicknesses, line widths, warpage, bond strengths or physical defects · CPC title

• H10P74/27

  Structural arrangements therefor · CPC title

• H10P76/4085 Primary

  characterised by the processes involved to create the masks · CPC title

• H10P50/695

  characterised by the process involved to create the mask, e.g. lift-off masks or sidewalls or to modify the mask · CPC title

• H10P50/642

  Chemical etching · CPC title