Methods for fabricating integrated circuits using directed self-assembly including a substantially periodic array of topographical features that includes etch resistant topographical features for transferability control

Patent metadata

Field	Value
Publication number	US-2016247686-A1
Application number	US-201514630676-A
Country	US
Kind code	A1
Filing date	Feb 25, 2015
Priority date	Feb 25, 2015
Publication date	Aug 25, 2016
Grant date	—

Abstract

Methods for fabricating integrated circuits are provided. In one example, a method for fabricating an integrated circuit includes forming a substantially periodic array of a plurality of topographical features including a plurality of etch resistant topographical features and at least one graphoepitaxy feature. The plurality of etch resistant topographical features define a plurality of etch resistant confinement wells and the at least one graphoepitaxy feature defines a graphoepitaxy confinement well that has a different size and/or shape than the etch resistant confinement wells. A block copolymer is deposited into the confinement wells. The block copolymer is phase separated into an etchable phase and an etch resistant phase. The etch resistant topographical features direct the etch resistant phase to form an etch resistant plug in each of the etch resistant confinement wells.

First claim

What is claimed is:

1 . A method for fabricating an integrated circuit comprising:
forming a substantially periodic array of a plurality of topographical features comprising a plurality of etch resistant topographical features and at least one graphoepitaxy feature that overlie a semiconductor substrate, wherein the plurality of etch resistant topographical features define a plurality of etch resistant confinement wells and the at least one graphoepitaxy feature defines a graphoepitaxy confinement well that has a different size and/or shape than the etch resistant confinement wells for producing an etch-transferrable directed self-assembly (DSA) result; depositing a block copolymer into the etch resistant confinement wells and the graphoepitaxy confinement well; and phase separating the block copolymer into an etchable phase and an etch resistant phase, wherein the etch resistant topographical features direct the etch resistant phase to form an etch resistant plug in each of the etch resistant confinement wells.

2 . The method of claim 1 , wherein forming the substantially periodic array comprises forming the etch resistant confinement wells and the graphoepitaxy confinement well arranged in a substantially periodic parallel line array.

3 . The method of claim 1 , wherein forming the substantially periodic array comprises forming the etch resistant confinement wells and the graphoepitaxy confinement well arranged in a substantially periodic regular-row-column array.

4 . The method of claim 1 , wherein forming the substantially periodic array comprises forming the etch resistant confinement wells and the graphoepitaxy confinement well arranged in a substantially periodic hexagonal array.

5 . The method of claim 1 , wherein forming the substantially periodic array comprises forming the substantially periodic array having a periodic pitch of from about 10 to about 40 nm.

6 . The method of claim 1 , wherein phase separating comprises forming at least one of the etch resistant plugs extending laterally substantially across at least one of the etch resistant confinement wells.

7 . The method of claim 1 , wherein phase separating comprises forming at least one of the etch resistant plugs surrounding a corresponding portion of the etchable phase.

8 . The method of claim 1 , wherein forming the substantially periodic array comprises forming each of the etch resistant confinement wells having a predetermined depth that facilitates directing formation of the etch resistant plugs.

9 . The method of claim 8 , wherein forming the substantially periodic array comprises forming each of the etch resistant confinement wells having the predetermined depth defined by computational simulations.

10 . The method of claim 8 , wherein forming the substantially periodic array comprises comprise forming each of the etch resistant confinement wells having the predetermined depth defined experimentally.

11 . The method of claim 1 , wherein forming the substantially periodic array comprises forming each of the etch resistant confinement wells having a predetermined width that facilitates directing formation of the etch resistant plugs.

12 . The method of claim 11 , wherein forming the substantially periodic array comprises comprise forming each of the etch resistant confinement wells having the predetermined width defined by computational simulations.

13 . The method of claim 11 , wherein forming the substantially periodic array comprises forming each of the etch resistant confinement wells having the predetermined width defined experimentally.

14 . The method of claim 1 , wherein depositing the block copolymer comprises depositing the block copolymer having a volume fraction minority phase and a volume fraction majority phase, and wherein phase separating the block copolymer comprises phase separating the block copolymer into the volume fraction majority phase as the etch resistant phase and the volume fraction minority phase as the etchable phase.

15 . A method for fabricating an integrated circuit comprising:
forming a substantially periodic array of topographical features comprising a plurality of etch resistant topographical features and at least one graphoepitaxy feature that overlie a semiconductor substrate, wherein the plurality of etch resistant topographical features define a plurality of etch resistant confinement wells and the at least one graphoepitaxy feature defines a graphoepitaxy confinement well; filling the graphoepitaxy confinement well with a first quantity of a block copolymer; filling the etch resistant confinement wells with a second quantity of the block copolymer; phase separating the first quantity of the block copolymer into a first etchable phase and a first etch resistant phase, wherein the at least one graphoepitaxy feature directs the first etchable phase to extend longitudinally substantially through the graphoepitaxy confinement well; and phase separating the second quantity of the block copolymer into a second etchable phase and a second etch resistant phase, wherein the etch resistant topographical features direct the second etch resistant phase to obstruct the second etchable phase from extending longitudinally substantially through each of the etch resistant confinement wells.

16 . The method of claim 15 , wherein phase separating the first quantity of the block copolymer comprises directing the first etchable phase to form an etchable cylinder that extends longitudinally substantially through the graphoepitaxy confinement well.

17 . The method of claim 15 , further comprising:
depositing a neutral brush layer overlying the semiconductor substrate, wherein forming the substantially periodic array comprises forming the plurality of topographical features overlying the neutral brush layer.

18 . The method of claim 15 , wherein phase separating the second quantity of the block copolymer comprises directing the second etch resistant phase with the etch resistant topographical features to form an etch resistant plug in each of the etch resistant confinement wells, and wherein the method further comprises:
etching the block copolymer after phase separating the first and second quantities to remove the first etchable phase from the graphoepitaxy confinement well to form a first opening while obstructing etching of the second quantity of the block copolymer with the etch resistant plugs to prevent forming an opening through any of the etch resistant confinement wells, thereby defining an etch mask.

19 . The method of claim 18 , further comprising:
etching a second opening into an underlying layer using the etch mask, wherein the second opening is aligned with the first opening.

20 . A method for fabricating an integrated circuit comprising:
forming a plurality of topographical features overlying a semiconductor substrate to define a plurality of confinement wells arranged in a substantially periodic parallel line array, wherein the plurality of topographical features comprises at least one graphoepitaxy feature and a plurality of etch resistant topographical features, wherein the plurality of confinement wells comprises a graphoepitaxy confinement well that is defined by the at least one graphoepitaxy feature and etch resistant confinement wells that are defined by the etch resistant topographical features, and wherein one of the etch resistant confinement wells is directly coupled to the graphoepitaxy confinement well so as to define a modified confinement well that has an etc

Assignees

• Globalfoundries Inc

Inventors

• Latypov Azat
• Coskun Tamer
• Preil Moshe

Classifications

• H10P76/20 Primary

  of masks comprising organic materials · CPC title

• H10P50/695 Primary

  characterised by the process involved to create the mask, e.g. lift-off masks or sidewalls or to modify the mask · CPC title

• H01L21/3086 Primary

  Electricity · mapped topic

• G03F7/0002

  Lithographic processes using patterning methods other than those involving the exposure to radiation, e.g. by stamping · CPC title