Semiconductor device

Patent metadata

Field	Value
Publication number	US-10134756-B2
Application number	US-201715608076-A
Country	US
Kind code	B2
Filing date	May 30, 2017
Priority date	Dec 9, 2016
Publication date	Nov 20, 2018
Grant date	Nov 20, 2018

Abstract

A semiconductor device includes a plurality of cell gate electrodes on a semiconductor substrate. End portions of the cell gate electrodes include stepped-pad regions that extend in a direction parallel to a surface of the semiconductor substrate. Vertical structures are on the semiconductor substrate and pass through the plurality of cell gate electrodes. The vertical structures respectively include a channel layer. Upper peripheral transistors are disposed on the semiconductor substrate. The upper peripheral transistors include an upper peripheral gate electrode at a level higher than a level of the plurality of cell gate electrodes, body patterns passing through the upper peripheral gate electrode and electrically connected to the pad regions, and gate dielectric layers between the upper peripheral gate electrode and the body patterns.

First claim

What is claimed is:

1. A semiconductor device, comprising:
a semiconductor substrate;
a plurality of cell gate electrodes on the semiconductor substrate, the plurality of cell gate electrodes being stacked on top of each other and extending in a direction parallel to a surface of the semiconductor substrate, the plurality of cell gate electrodes including pad regions arranged in a stepped manner at end portions of the plurality of cell gate electrodes;
vertical structures on the semiconductor substrate, the vertical structures passing through the plurality of cell gate electrodes, and the vertical structures respectively including a channel layer; and
upper peripheral transistors on the semiconductor substrate,
the upper peripheral transistors including an upper peripheral gate electrode at a level higher than a level of the plurality of cell gate electrodes, body patterns passing through the upper peripheral gate electrode and being electrically connected to the pad regions, and gate dielectric layers between the upper peripheral gate electrode and the body patterns.

2. The semiconductor device of claim 1 , wherein a distance between the upper peripheral gate electrode and a surface of the semiconductor substrate is greater than a distance between upper surfaces of the vertical structures and the surface of the semiconductor substrate.

3. The semiconductor device of claim 1 , further comprising:
lower contact plugs on the pad regions,
wherein the lower contact plugs and the pad regions contact each other to form an interface.

4. The semiconductor device of claim 3 , wherein
upper surfaces of the lower contact plugs are coplanar with each other, and
the upper surfaces of the lower contact plugs are at a level higher than a level of upper surfaces of the vertical structures.

5. The semiconductor device of claim 3 , further comprising:
a connection pattern on the lower contact plugs,
wherein the connection pattern electrically connects the body patterns and the lower contact plugs to each other.

6. The semiconductor device of claim 1 , wherein
the body patterns respectively include a lower impurity region and an upper impurity region having N-type conductivity, and a channel region between the lower impurity region and the upper impurity region and having P-type conductivity, and
the channel region opposes the upper peripheral gate electrode.

7. The semiconductor device of claim 1 , further comprising:
an upper gate electrode on the plurality of cell gate electrodes.

8. The semiconductor device of claim 7 , wherein the upper gate electrode and the upper peripheral gate electrode are coplanar.

9. The semiconductor device of claim 7 , wherein a material of the upper gate electrode is the same as a material of the upper peripheral gate electrode.

10. The semiconductor device of claim 9 , wherein the material of the upper gate electrode is different than a material of the plurality of cell gate electrodes.

11. A semiconductor device, comprising:
a semiconductor substrate;
a memory cell array on the semiconductor substrate, the memory cell array including first word lines and vertical structures, the first word lines being stacked on top of each other in a direction perpendicular to a surface of the semiconductor substrate, the vertical structures passing through the first word lines,
the vertical structures respectively including a channel layer and a drain connected to an upper region of the channel layer,
the first word lines including stepped-first pad regions at end portions of the first word lines, the stepped-first pad regions extending in a direction parallel to the surface of the semiconductor substrate; and
a peripheral circuit on the semiconductor substrate, the peripheral circuit including an upper circuit electrically connected to the stepped-first pad regions,
the upper circuit including an upper peripheral gate electrode at a level higher than a level of the first word lines,
the upper circuit including body patterns passing through the upper peripheral gate electrode and electrically connected to the stepped-first pad regions, and
the upper circuit including an upper gate dielectric layer between the upper peripheral gate electrode and the body patterns.

12. The semiconductor device of claim 11 , further comprising:
second word lines on the semiconductor substrate, wherein
the first word lines and the second word lines are coplanar
the second word lines include stepped-second pad regions at end portions of the second word lines, and
the stepped-second pad regions extend the direction parallel to the surface of the semiconductor substrate.

13. The semiconductor device of claim 12 , further comprising:
first lower contact plugs on the stepped-first pad regions;
second lower contact plugs on the stepped-second pad regions; and
connection patterns connected to a first lower contact plug and a second lower contact plug, wherein
the first lower contact plugs include the first lower contact plug,
the second lower contact plugs include the second lower contact plug,
a height of the first lower contact plug is the same as a height of the second lower contact plug, and
the body patterns are on the connection patterns.

14. The semiconductor device of claim 12 , further comprising:
a string select line on the first word lines, wherein
the string select line and the upper peripheral gate electrode are coplanar.

15. The semiconductor device of claim 14 , wherein
the peripheral circuit further includes a lower circuit,
the lower circuit does not overlap the first word lines and the stepped-first pad regions,
the lower circuit is closer to the semiconductor substrate than the upper circuit, and
the lower circuit is electrically connected to the string select line.

16. A semiconductor device, comprising:
a substrate;
a plurality of word lines stacked on top of each other on the substrate and spaced apart from each other in a vertical direction compared to a top surface of the substrate, a width of the plurality of word lines decreasing as a distance of the plurality of word lines from the top surface of the substrate is increased, the plurality of word lines including stepped-pad regions at end portions of the plurality of word lines;
a plurality of vertical structures extending through a portion of the plurality of word lines in the vertical direction;
lower contact plugs on the stepped-pad regions of the plurality of word lines, the lower contact plugs extending in the vertical direction;
upper peripheral transistors on the lower contact plugs; and
an upper peripheral wiring on the upper peripheral transistors.

17. The semiconductor device of claim 16 , wherein
a level of an upper surface of the lower contact plugs above the upper surface of the substrate is greater than a level of an upper surface of the plurality of vertical structures above the upper surface of the substrate; and
the plurality of vertical structures respectively include a channel layer.

18. The semiconductor device of claim 16 , wherein the upper peripheral transistors include:
an upper peripheral gate electrode extending parallel to the top surface of the substrate; and
body patterns passing through the upper peripheral gate electrode; and
gate dielectric layers between the upper peripheral gate electrode and the body patterns.

19. The semiconductor device of claim 16 , further comprising:
a lower peripheral transistor on the substrate; and
a lower peripheral contact plug connected to a

Assignees

• Shim Sun Il
• Choi Seung Wook
• Samsung Electronics Co Ltd

Inventors

• Shim Sun Il
• Choi Seung Wook

Classifications

• H10W20/42

  Vias, e.g. via plugs · CPC title

• H01L23/5226

  Electricity · mapped topic

• H01L27/11582 Primary

  Electricity · mapped topic

• H10B41/50

  characterised by the boundary region between the core region and the peripheral circuit region · CPC title

• H10B43/40

  characterised by the peripheral circuit region · CPC title