Apparatuses and methods including memory and operation of same

Patent metadata

Field	Value
Publication number	US-10134470-B2
Application number	US-201514932746-A
Country	US
Kind code	B2
Filing date	Nov 4, 2015
Priority date	Nov 4, 2015
Publication date	Nov 20, 2018
Grant date	Nov 20, 2018

Abstract

Disclosed herein is a memory cell. The memory cell may act both as a combined selector device and memory element. The memory cell may be programmed by applying write pulses having different polarities. Different polarities of the write pulses may program different logic states into the memory cell. The memory cell may be read by read pulses all having the same polarity. The logic state of the memory cell may be detected by observing different threshold voltages when the read pulses are applied. The different threshold voltages may be responsive to the different polarities of the write pulses.

First claim

What is claimed is:

1. A method, comprising:
applying a read pulse having a first polarity to a memory cell, wherein a first or a second logic state is written to the memory cell, wherein the first logic state is written responsive to a write pulse having the first polarity and the second logic state is written responsive to the write pulse having a second polarity, wherein the read pulse has a magnitude less than a magnitude of the write pulse;
sensing a current through the memory cell responsive to the read pulse; and
determining the memory cell is in the first or second logic state, based on the current through the memory cell,
wherein the memory cell is determined to be in the second logic state if the current through the memory cell is below a threshold current and the memory cell is determined to be in the first logic state if the current through the memory cell is equal to or above the threshold current, and
wherein the magnitude of the read pulse is between a magnitude of a first threshold voltage of the memory cell causing the current that is equal to or above the threshold current and a magnitude of a second threshold voltage of the memory cell which causes the current that is below the threshold current.

2. The method of claim 1 , wherein the current is sensed with a sense amplifier.

3. The method of claim 1 , wherein a duration of the read and write pulses is between 1 nanosecond and 1 microsecond.

4. The method of claim 1 , further comprising writing a desired logic state to the memory cell with the write pulse having the first polarity or the second polarity when the logic state of the memory cell is determined to be in an undesired logic state.

5. The method of claim 1 , wherein applying the read pulse to the memory cell is destructive to the first or second logic state.

6. The method of claim 1 , further comprising providing a negative voltage to a first memory access line coupled to the memory cell and providing a positive voltage to a second memory access line coupled to the memory cell to provide the write pulse having the first polarity.

7. The method of claim 1 , further comprising providing a first non-negative voltage to a first memory access line coupled to the memory cell and providing a second non-negative voltage to a second memory access line coupled to the memory cell to provide the write pulse having the first polarity, wherein the second non-negative voltage is greater than the first non-negative voltage.

8. A method, comprising:
applying a first read pulse having a first polarity to a memory cell, wherein the memory cell was programmed to a logic state with a write pulse having the first polarity or a second polarity;
sensing a first threshold voltage of the memory cell responsive to the first read pulse;
applying a second read pulse having the first polarity to the memory cell;
sensing a second threshold voltage of the memory cell responsive to the second read pulse;
calculating a difference between the first threshold voltage and the second threshold voltage; and
determining the logic state of the memory cell, wherein the logic state is determined to be a first state when the difference is below a threshold value and the logic state is determined to be a second state when the difference is above the threshold value.

9. The method of claim 8 , wherein the first and second read pulses are ramped voltage pulses.

10. The method of claim 9 , wherein a voltage of the ramped voltage pulses is increased linearly.

11. The method of claim 9 , wherein a voltage of the ramped voltage pulses is increased non-linearly.

12. The method of claim 9 , further comprising reprogramming the memory cell to the logic state after the second read pulse.

Assignees

• Micron Technology Inc

Inventors

• Tortorelli Innocenzo
• Tang Stephen
• Papagianni Christina

Classifications

• G11C2213/77

  Array wherein the memory element being directly connected to the bit lines and word lines without any access device being used · CPC title

• G11C7/1078

  Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits · CPC title

• G11C11/5678

  using amorphous/crystalline phase transition storage elements · CPC title

• G11C7/06

  Sense amplifiers; Associated circuits {, e.g. timing or triggering circuits} · CPC title

• G11C2013/0073

  Write using bi-directional cell biasing · CPC title