Double-polarity memory read

Patent metadata

Field	Value
Publication number	US-9799381-B1
Application number	US-201615278983-A
Country	US
Kind code	B1
Filing date	Sep 28, 2016
Priority date	Sep 28, 2016
Publication date	Oct 24, 2017
Grant date	Oct 24, 2017

Abstract

Circuits, systems, and methods for double-polarity reading of double-polarity stored data information are described. In one embodiment, a method involves applying a first voltage with a first polarity to a plurality of the memory cells. The method involves applying a second voltage with a second polarity to one or more of the plurality of memory cells. The method involves detecting electrical responses of the one or more memory cells to the first voltage and the second voltage. The method also involves determining a logic state of the one or more memory cells based on the electrical responses of the one or more memory cells to the first voltage and the second voltage.

First claim

What is claimed is:

1. A circuit for accessing an array of memory cells, the circuit comprising:
access circuitry to:
apply a first voltage with a first polarity to a plurality of the memory cells, wherein the application of the first voltage with the first polarity includes application of a more positive voltage to a first terminal than to a second terminal of a given memory cell of the array, and
apply a second voltage with a second polarity to one or more of the plurality of the memory cells, wherein the application of the second voltage with the second polarity includes application of a more positive voltage to the second terminal than to the first terminal of the given memory cell of the array; and

sense circuitry to detect electrical responses of the one or more memory cells to the first voltage and the second voltage;
wherein the access circuitry is to determine a logic state of the one or more memory cells based on the electrical responses of the one or more memory cells to the first voltage and the second voltage.

2. The circuit of claim 1 , wherein:
the access circuitry is to determine whether the given memory cell of the array is in a first logic state or whether the given memory cell's logic state is inconclusive based on a first electrical response to the first voltage.

3. The circuit of claim 2 , wherein:
the access circuitry is to apply the second voltage with the second polarity to the given memory cell in response to a determination that the given memory cell's logic state is inconclusive based on the first electrical response.

4. The circuit of claim 2 , wherein:
the access circuitry is to determine that the given memory cell is in the first logic state or a second logic state based on a second electrical response to the second voltage at the second polarity.

5. The circuit of claim 2 , wherein:
the sense circuitry is to detect first current through the given memory cell in response to the first voltage; and
wherein the access circuitry is to determine the given memory cell is in the first logic state based on detection that a magnitude of the first current is greater than or equal to a first threshold.

6. The circuit of claim 2 , wherein:
the sense circuitry is to detect first current through the given memory cell in response to the first voltage; and
wherein the access circuitry is to determine the given memory cell's logic state is inconclusive based on detection that a magnitude of the first current is less than a first threshold.

7. The circuit of claim 6 , wherein:
the sense circuitry is to detect second current through the given memory cell in response to the second voltage; and
wherein the access circuitry is to determine the given memory cell is at the first logic state based on detection that a magnitude of the second current is less than a second threshold.

8. The circuit of claim 6 , wherein:
the sense circuitry is to detect second current through the given memory cell in response to the second voltage; and
wherein the access circuitry is to determine the given memory cell is at a second logic state based on detection that a magnitude of the second current is greater than or equal to a second threshold.

9. The circuit of claim 1 , wherein:
the access circuitry is to:
apply the first voltage having a first magnitude; and
apply the second voltage having a second magnitude greater than the first magnitude.

10. The circuit of claim 9 , wherein:
the sense circuitry is to detect a threshold voltage for a given memory cell of the one or more memory cells in response to an applied voltage, wherein the applied voltage is one of the first or second voltages;
wherein if the given memory cell is programmed with a same polarity as the applied voltage, the sense circuitry is to detect that the threshold voltage's magnitude is in a first range; and
wherein if the given memory cell is programmed with a different polarity than the applied voltage, the sense circuitry is to detect that the threshold voltage's magnitude is in a second range.

11. The circuit of claim 10 , wherein an upper end of the first range overlaps a lower end of the second range.

12. The circuit of claim 10 , wherein:
the access circuitry is to apply the first voltage having the first magnitude that is lower than an expected lowest magnitude of the second range.

13. The circuit of claim 10 , wherein:
the access circuitry is to apply the second voltage having the second magnitude that is higher than an expected highest magnitude of the second range.

14. The circuit of claim 1 , wherein:
the access circuitry is to refresh one or more of the memory cells via the application of the first voltage and the second voltage.

15. The circuit of claim 2 , wherein:
the access circuitry is to mask a given memory cell of the array from the second voltage based on a determination that the given memory cell is in the first logic state.

16. The circuit of claim 1 , wherein:
the application of the second voltage is based on a triggering event.

17. The circuit of claim 16 , wherein the triggering event comprises a determination that an error rate is greater than or equal to an error threshold.

18. A system comprising:
a memory comprising an array of memory cells; and
a circuit communicatively coupled with the array of memory cells, the circuit comprising:
access circuitry to:
apply a first voltage with a first polarity to a plurality of the memory cells, wherein the application of the first voltage with the first polarity includes application of a more positive voltage to a first terminal than to a second terminal of a given memory cell of the array, and
apply a second voltage with a second polarity to one or more of the plurality of memory cells, wherein the application of the second voltage with the second polarity includes application of a more positive voltage to the second terminal than to the first terminal of the given memory cell of the array; and

sense circuitry to detect electrical responses of the one or more memory cells to the first voltage and the second voltage;
wherein the access circuitry is to determine a logic state of the one or more memory cells based on the electrical responses of the one or more memory cells to the first voltage and the second voltage.

19. The system of claim 18 , further comprising any of a display communicatively coupled to the memory, a network interface communicatively coupled to the memory, or a battery coupled to provide power to the system.

20. A method of accessing an array of memory cells, the method comprising:
applying a first voltage with a first polarity to a plurality of the memory cells, wherein applying the first voltage with the first polarity includes applying a more positive voltage to a first terminal than to a second terminal of a given memory cell of the array;
applying, to one or more of the plurality of memory cells, a second voltage with a second polarity, wherein applying the second voltage with the second polarity includes applying a more positive voltage to the second terminal than to the first terminal of the given memory cell of the array;
detecting electrical responses of the one or more memory cells to the first voltage and the second voltage; and
determining a logic state of the one or more memory cells based on the electrical responses of the one or more memory cells to the first voltage and the second voltage.

21. The method of claim 20 , wherein determining the logic state of the one or more

Assignees

• Intel Corp

Inventors

• Tortorelli Innocenzo
• Pio Federico

Classifications

• G11C13/003 Primary

  Cell access · CPC title

• G11C7/062

  Differential amplifiers of non-latching type, e.g. comparators, long-tailed pairs · CPC title

• G11C7/22 Primary

  Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management · CPC title

• G11C13/0004

  comprising amorphous/crystalline phase transition cells · CPC title

• G11C2213/73

  Array where access device function, e.g. diode function, being merged with memorizing function of memory element · CPC title