Enhanced erasing of two-terminal memory

Patent metadata

Field	Value
Publication number	US-9805794-B1
Application number	US-201514716386-A
Country	US
Kind code	B1
Filing date	May 19, 2015
Priority date	May 19, 2015
Publication date	Oct 31, 2017
Grant date	Oct 31, 2017

Abstract

Two-terminal memory can be set to a first state (e.g., conductive state) in response to a program pulse, or set a second state (e.g., resistive state) in response to an erase pulse. These pulses generally provide a voltage difference between the two terminals of the memory cell. Certain electrical characteristics associated with the pulses can be manipulated in order to enhance the efficacy of the pulse. For example, the pulse can be enhanced or improved to reduce power-consumption associated with the pulse, reduce a number of pulses used to successfully set the state of the memory cell, reduce wear or damage to the memory cell, or to improve Ion or Ioff distribution associated with changing the state of the memory cell.

First claim

What is claimed is:

1. A memory device, comprising:
an array of memory cells comprising a two-terminal memory cell that includes an interface layer situated between a top electrode and a bottom electrode;
a controller device that asserts an erase pulse that erases the two-terminal memory cell characterized by setting the two-terminal memory cell to a resistive state; and
an optimization component that optimizes the erase pulse, asserted by the controller device, based on a first algorithm that asserts a lower magnitude voltage during a first period of the erase pulse and a higher magnitude voltage during a second period of the erase pulse, wherein the lower magnitude voltage is substantially constant during the first period, wherein the higher magnitude voltage is greater in magnitude than the lower magnitude voltage, and wherein the first period is significantly longer than the second period.

2. The memory device of claim 1 , wherein the second period of the erase pulse causes particles of a conductive filament formed in the interface layer to retreat toward an active metal layer and causes a transition of the two-terminal memory cell from a conductive state to the resistive state.

3. The memory device of claim 2 , wherein the lower magnitude voltage has a magnitude sufficient to ionize particles of the conductive filament in response to joule heat resulting from application of the lower magnitude voltage.

4. The memory device of claim 1 , wherein the lower magnitude voltage is about one volt in magnitude lower than the higher magnitude voltage.

5. The memory device of claim 1 , wherein the first period is about 20 microseconds and the second period is about 100 nanoseconds.

6. A method, comprising:
receiving, by a controller of a memory device, an instruction to erase a two-terminal memory cell comprising an interface layer situated between a first terminal and a second terminal, wherein the instruction to erase relates to setting the two-terminal memory cell to a resistive state;
determining, by the controller, a first set of electrical characteristics to be applied during a first period of an erase pulse that, when applied to the two-terminal memory cell, sets the two-terminal memory cell to the resistive state, wherein the first set of electrical characteristics indicate a first voltage sufficient to facilitate ionization of active metal particles included in the interface layer of the two-terminal memory cell, and wherein the ionization of the active metal particles is in response to joule-heating produced during the first period; and
determining, by the controller, a second set of electrical characteristics that differ from the first set of electrical characteristics and are associated with a second period of the erase pulse, wherein the second set of electrical characteristics indicate a second voltage sufficient to facilitate driving the active metal particles at least in part toward an active metal layer of the two-terminal memory cell, wherein the second voltage is greater than the first voltage and the first period is significantly greater than the second period.

7. The method of claim 6 , wherein the determining the first set of electrical characteristics or the second set of electrical characteristics is based on a determination that the first set or the second set of electrical characteristics set the two-terminal memory cell to the resistive state with reduced power consumption, with a reduced number of erase pulses, or with reduced wear on the two-terminal memory cell.

8. The method of claim 6 , wherein the first set of electrical characteristics includes a joule-heat portion characterized by asserting the first voltage at the first terminal or the second terminal.

9. The method of claim 6 , wherein the first set of electrical characteristics includes a ramping portion characterized by ramping up to the first voltage at the first terminal or the second terminal during the first period of the erase pulse.

10. The method of claim 6 , wherein the second set of electrical characteristics includes a high-voltage kick characterized by asserting the second voltage at the first terminal or the second terminal.

11. The method of claim 6 , wherein the second set of electrical characteristics includes another ramping portion characterized by ramping down from a peak magnitude voltage at the first terminal or the second terminal during the second period of the erase pulse.

12. The method of claim 6 , wherein the first period and the second period exclude ramp times.

13. The method of claim 6 , wherein the driving of the active metal particles is in response to an electric field produced during the second period.

14. The memory device of claim 1 , wherein the first period and the second period exclude ramp times.

15. A method, comprising:
receiving, by a controller of a memory device, an instruction to erase a two-terminal memory cell comprising an interface layer situated between a first terminal and a second terminal, wherein the instruction to erase relates to setting the two-terminal memory cell to a resistive state;
determining, by the controller, a first set of electrical characteristics to be applied during a first period of an erase pulse, wherein the erase pulse is determined to be suitable to set the two-terminal memory cell to the resistive state, and wherein the first set of electrical characteristics comprises application of a lower magnitude voltage that is substantially constant during the first period;
determining, by the controller, a second set of electrical characteristics to be applied during a second period of the erase pulse, wherein the second set of electrical characteristics comprises application of a higher magnitude voltage that is greater in magnitude than the lower magnitude voltage; and
asserting, by the controller, the erase pulse having the lower magnitude voltage during the first period and the higher magnitude voltage during the second period, wherein the first period is greater than the second period by at least a factor of about ten.

16. The method of claim 15 , wherein the first period, during which the lower magnitude voltage is substantially constant, is about 20 microseconds.

17. The method of claim 15 , wherein the higher magnitude voltage is substantially constant during the second period and the second period is about 100 nanoseconds.

18. The method of claim 15 , wherein a difference in magnitude between the lower magnitude voltage that is substantially constant during the first period and the higher magnitude voltage that is substantially constant during the second period is about one volt.

19. The method of claim 15 , further comprising:
determining, in response to a read pulse, that the two-terminal memory cell is not set to the resistive state; and
applying, to the two-terminal memory cell, a second erase pulse comprising:
a second lower magnitude voltage that has a first magnitude differing from the lower magnitude voltage and is applied for a third period of the second erase pulse that is substantially equal in length to the first period; and
a second higher magnitude voltage that has a second magnitude differing from the higher magnitude voltage and is applied for a fourth period of the second erase pulse that is substantially equal in length to the second period.

20. The method of claim 19 , wherein the second lower magnitude voltage is substantially constant during the third period and the second higher magnitude voltage is substantially constant during the

Assignees

• Crossbar Inc

Inventors

• Li Zhi
• Kumar Tanmay
• Jo Sung Hyun

Classifications

• G11C11/5685

  using storage elements comprising metal oxide memory material, e.g. perovskites · CPC title

• G11C13/0097 Primary

  Erasing, e.g. resetting, circuits or methods · CPC title

• G11C13/0007

  comprising metal oxide memory material, e.g. perovskites · CPC title

• G11C13/0011

  comprising conductive bridging RAM [CBRAM] or programming metallization cells [PMCs] · CPC title

• G11C2013/0092

  Write characterized by the shape, e.g. form, length, amplitude of the write pulse · CPC title