Three dimensional memory array with select device

Patent metadata

Field	Value
Publication number	US-9728584-B2
Application number	US-201313915302-A
Country	US
Kind code	B2
Filing date	Jun 11, 2013
Priority date	Jun 11, 2013
Publication date	Aug 8, 2017
Grant date	Aug 8, 2017

Abstract

Three dimensional memory arrays and methods of forming the same are provided. An example three dimensional memory array can include a stack comprising a plurality of first conductive lines separated from one another by at least an insulation material, and at least one conductive extension arranged to extend substantially perpendicular to the plurality of first conductive lines such that the at least one conductive extension intersects each of the plurality of first conductive lines. Storage element material is arranged around the at least one conductive extension, and a select device is arranged around the storage element material. The storage element material is radially adjacent an insulation material separating the plurality of first conductive lines, and the plurality of materials arranged around the storage element material are radially adjacent each of the plurality of first conductive lines.

First claim

What is claimed is:

1. A three dimensional memory array, comprising:
a stack comprising a plurality of first conductive lines separated from one another by at least an insulation material;
at least one conductive extension arranged to extend substantially perpendicular to the plurality of first conductive lines, such that the at least one conductive extension intersects each of the plurality of first conductive lines;
storage element material arranged around the at least one conductive extension;
a buffer material disposed concentrically between and in physical contact with the at least one conductive extension and the storage element; and
a select device arranged around the storage element material, the select device including an inner concentric conductor material in physical contact with the storage element material at two discrete locations and an outer concentric non-metallic material arranged around the inner concentric conductor material such that the outer concentric non-metallic material is in physical contact with a first surface, a second surface, and a third surface of the inner concentric conductor material, wherein the storage element material is radially adjacent an insulation material separating the plurality of first conductive lines, and a plurality of materials comprising the select device are arranged annularly around the storage element material and are radially adjacent each of the plurality of first conductive lines.

2. The memory array of claim 1 , wherein the outer concentric non-metallic material includes a semiconductor material.

3. The memory array of claim 1 , wherein the outer concentric non-metallic material includes an insulator material.

4. The memory array of claim 1 , wherein the outer concentric non-metallic material includes a lamellar stack that includes alternating semiconductor and insulator materials.

5. The memory array of claim 1 , wherein the plurality of first conductive lines and inner concentric conductor material include a same metal material, and the outer concentric non-metallic material includes silicon.

6. The memory array of claim 1 , wherein the plurality of first conductive lines and inner concentric conductor material include titanium nitride (TiN).

7. The memory array of claim 1 , wherein the select device is a metal-insulator-metal select device.

8. The memory array of claim 1 , wherein the select device is a metal-semiconductor-metal select device.

9. The memory array of claim 1 , wherein the select device is an ovonic threshold switch.

10. The memory array of claim 1 , further comprising second buffer material arranged around the storage element material, the second buffer material being located between the select device and the storage element material.

11. A three dimensional memory array, comprising:
a stack comprising a plurality of first conductive lines separated from one another by at least an insulation material;
at least one conductive extension arranged to extend substantially perpendicular to the plurality of first conductive lines such that the at least one conductive extension intersects each of the plurality of first conductive lines;
buffer material, storage element material, conductor material, and semiconductor material arranged around the at least one conductive extension,
wherein the buffer material is disposed concentrically between and in physical contact with the at least one conductive extension and the storage element material;
and wherein a first instance of the conductor material is adjacent a first instance of the semiconductor material,
and the first instance of the conductor material and the first instance of the semiconductor material are isolated from other instances of the conductor material and the semiconductor material, and
wherein the at least one conductive extension, buffer material, and storage element material are contiguous between the first and other instances of the conductor material and the semiconductor material,
and at least two portions of the storage element material are in physical contact with the first and other instances of the conductor material, and
wherein the semiconductor material is disposed on at least a first surface, a second surface, and a third surface of the conductor material.

12. The memory array of claim 11 , wherein the buffer material, storage element material, conductor material, and semiconductor material are concentrically arranged around the at least one conductive extension.

13. The memory array of claim 11 , wherein the conductor material is arranged between the semiconductor material and the at least one conductive extension.

14. The memory array of claim 11 , wherein the first instances of the conductor material and the semiconductor material are isolated from the second instances of the conductor material and the semiconductor material by at least the insulation material separating the plurality of first conductive lines.

15. The memory array of claim 11 , wherein the buffer material is arranged between the storage element material and the at least one conductive extension.

16. The memory array of claim 11 , further comprising a plurality of second conductive lines arranged to extend substantially perpendicular to the plurality of first conductive lines at different planes than planes at which the plurality of first conductive lines are arranged, and arranged to extend substantially perpendicular to the at least one conductive extension,
wherein the at least one conductive extension is in contact with at least one of the plurality of second conductive lines.

17. A three dimensional memory array, comprising:
a stack of alternating levels of conductive lines and insulation material;
a conductive extension arranged to extend substantially perpendicular to the conductive lines, such that the conductive extension intersects each of the conductive lines;
storage element material concentrically arranged around a length of the conductive extension, the storage element material being contiguous along the length of the conductive extension;
a buffer material comprising an ion diffusion barrier disposed concentrically between and in physical contact with the conductive extension and the storage element material;
and a plurality of discrete select devices, the plurality of discrete select devices each having a ring geometry, a respective one of the plurality of discrete select devices being located adjacent a respective conductive line, and each of the plurality of discrete select devices, wherein each of the plurality of discrete select devices includes a non-metallic material at an outside diameter of the ring geometry and a conductor material at an inside diameter of the ring geometry and in physical contact with the storage element material at two discrete locations,
and wherein the non-metallic material is disposed on at least a first surface, a second surface, and a third surface of the conductor material.

18. The memory array of claim 17 , wherein the conductive lines and the conductor material at the inside diameter of the ring geometry comprise a same metal material.

19. The memory array of claim 17 , wherein the non-metallic material at the outside diameter of the ring geometry comprises a semiconductor material.

20. The memory array of claim 17 , wherein the non-metallic material at the outside diameter of the ring geometry comprises a dielectric material.

21. A method of forming a three dimensional memory array, comprising:
forming a stack com

Assignees

• Micron Technology Inc

Inventors

• Ramaswamy D V Nirmal
• Sills Scott E
• Sandhu Gurtej S

Classifications

• H01L27/249 Primary

  Electricity · mapped topic

• H01L45/146

  Electricity · mapped topic

• H01L45/085

  Electricity · mapped topic

• H01L45/06

  Electricity · mapped topic

• H01L45/08

  Electricity · mapped topic