Synchronous, internal clock edge alignment for integrated circuit testing

Patent metadata

Field	Value
Publication number	US-10128828-B2
Application number	US-201715485062-A
Country	US
Kind code	B2
Filing date	Apr 11, 2017
Priority date	Apr 20, 2016
Publication date	Nov 13, 2018
Grant date	Nov 13, 2018

Abstract

A synchronous clock edge alignment system and method increases detection coverage of transition delay faults that occur in logic circuits that have data released by a clock at an input of logic circuits internal to an integrated circuit and/or released at the output of the logic circuits when testing an integrated circuit. To increase detection coverage of inter-clock transition delay faults, in at least one embodiment, the synchronous clock edge alignment system and method align same transition type edges of internal data releasing clock signals, and at least two of the clock signals have different frequencies. By aligning the edges of the clock signals, transition delay faults that might otherwise not have occurred can be detected by, for example, a conventional circuit testing apparatus. Thus, aligning the edges of the clock signals increases detection of inter-clock transition delay faults.

First claim

What is claimed is:

1. An apparatus comprising:
an integrated circuit, the integrated circuit comprising:
logic circuits;
data gates, coupled to an input and an output of each of the logic circuits, to receive and store data to be released to and from the logic circuits; and
a synchronous clock edge alignment system coupled to the data gates, wherein the synchronous clock edge alignment system is configured to:
determine when synchronous clock signal edges of a same transition type are aligned, wherein at least two of the clock signals have different frequencies and the clock signals are internal to the integrated circuit;
provide gated clock signals to the data gates to release the stored data to and from the logic circuits when the edges of the clock signals are aligned; and
release the data into and out of the logic circuits to increase detection of transition delay faults in the logic circuits relative to detection of transition delay faults in the logic circuits that occur when the data is released and the edges of the clock signals are not aligned.

2. The apparatus of claim 1 further comprises:
T-flip flops having data input terminals to receive data and a set of the clock signals to clock input terminals of the T-flip flops;
wherein to determine when synchronous clock signal edges of a same transition type are aligned, the synchronous clock edge alignment system is configured to:
determine when next states of the data at output terminals of the T-flip flops are equivalent to a negation of current states of the data; and
identify an alignment of the clock signal edges when the next states of the data are equivalent to a negation of the current states of the data.

3. The apparatus of claim 1 further comprises:
T-flip flops having data input terminals to receive data and a set of the clock signals to clock input terminals of the T-flip flops;
wherein to determine when synchronous clock signal edges of a same transition type are aligned, the synchronous clock edge alignment system is configured to:
determine when next states of the data at output terminals of the T-flip flops are equivalent to current states of the data; and
identify an alignment of the clock signal edges when the next states of the data are equivalent to the current states of the data.

4. The apparatus of claim 2 wherein the clock signals include a master clock signal that determines a transition from the next states to the current states of the data, wherein the synchronous clock edge alignment system is further configured to
determine a least common multiple value of a number of pulses of the master clock signal between instances of when the edges of the clock signals are aligned; and
provide the gated signals to the logic circuits in the integrated circuit when a current number of pulses of the master clock since an immediately preceding occurrence of an alignment of the clock signals is equal to the least common multiple value.

5. The apparatus of claim 2 wherein the data received at respective terminals of the T-flip flops further comprises test pattern data to test functionality of the logic circuits of the integrated circuit.

6. The apparatus of claim 1 wherein the synchronous clock edge alignment system is further configured to:
detect entry into an upcoming data capture mode; and
initialize the synchronous clock edge alignment system to begin determination of when synchronous clock signal edges of the same transition type are aligned.

7. The apparatus of claim 1 wherein to enable the clock signals to be provided to the logic circuits in the integrated circuit, the synchronous clock edge alignment system is configured to:
generate a signal to control release of the clock signals to one or more inputs and one or more outputs of clock gates in the integrated circuit to synchronize insertion of data to logic that promulgate test data logic circuits of the integrated circuit.

8. The apparatus of claim 1 wherein the transition type is a member of a group consisting of (1) a positive edge transition and (2) a negative edge transition.

9. A method of increasing detection coverage of inter-clock transition delay faults comprising:
determining when synchronous clock signal edges of a same transition type are aligned, wherein at least two of clock signals of an integrated circuit have different frequencies and the clock signals are internal to an integrated circuit;
providing gated clock signals to logic circuits in the integrated circuit to release data into and out of the logic circuits when the edges of the clock signals are aligned; and
releasing the data into and out of the logic circuits to increase detection of transition delay faults in the logic circuits relative to detection of transition delay faults in the logic circuits that occur when the data is released and the edges of the clock signals are not aligned.

10. The method of claim 9 further comprises:
receiving data at respective terminals of a set of T-flip flops; and
applying a set of the clock signals to clock input terminals of the T-flip flops;
wherein determining when synchronous clock signal edges of a same transition type are aligned comprises:
determining when next states of the data at output terminals of the T-flip flops are equivalent to a negation of current states of the data; and
identifying an alignment of the clock signal edges when the next states of the data are equivalent to a negation of the current states of the data.

11. The method of claim 9 further comprises:
receiving data at respective terminals of a set of T-flip flops; and
applying a set of the clock signals to clock input terminals of the T-flip flops;
wherein determining when synchronous clock signal edges of a same transition type are aligned comprises:
determining when next states of the data at output terminals of the T-flip flops are equivalent to current states of the data; and
identifying an alignment of the clock signal edges when the next states of the data are equivalent to the current states of the data.

12. The method of claim 10 wherein the clock signals include a master clock signal that determines a transition from the next states to the current states of the data, the method further comprising:
determining a least common multiple value of a number of pulses of the master clock signal between instances of when the edges of the clock signals are aligned; and
enabling the clock signals to be provided to the circuits in the integrated circuit when a current number of pulses of the master clock since an immediately preceding occurrence of an alignment of the clock signals is equal to the least common multiple value.

13. The method of claim 10 wherein the data received at respective terminals of a set of T-flip flops further comprises test pattern data to test functionality of logic circuits of the integrated circuit.

14. The method of claim 9 further comprising:
detecting entry into an upcoming data capture mode; and
initializing determination of when synchronous clock signal edges of the same transition type are aligned.

15. The method of claim 9 wherein enabling the clock signals to be provided to the logic circuits in the integrated circuit comprises:
releasing the clock signals to one or more inputs and one or more outputs of clock gates in the integrated circuit to synchronize insertion of data to logic that promulgate test data logic circuits of the integrated circuit.

16. The method of claim 9 wherein the transition type is a member of a group consisting of (1) a positive edge transition and

Assignees

• Cirrus Logic Int Semiconductor Ltd
• Cirrus Logic Inc

Inventors

• Ramakrishnan Muraleedharan
• Kumar Bhoodev
• Oppula Vivek
• Geevarughese Niju Alex

Classifications

• G01R31/31726 Primary

  Synchronization, e.g. of test, clock or strobe signals; Signals in different clock domains; Generation of Vernier signals; Comparison and adjustment of the signals · CPC title

• H03K5/26 Primary

  the characteristic being duration, interval, position, frequency, or sequence · CPC title

• H03K5/135 Primary

  by the use of time reference signals, e.g. clock signals · CPC title