Low power adaptive synchronizer

Patent metadata

Field	Value
Publication number	US-9899992-B1
Application number	US-201615239217-A
Country	US
Kind code	B1
Filing date	Aug 17, 2016
Priority date	Aug 17, 2016
Publication date	Feb 20, 2018
Grant date	Feb 20, 2018

Abstract

A circuit adapts to the occurrence of metastable states. The circuit inhibits passing of the metastable state to circuits that follow, by clock gating the output stage. In order to determine whether or not to gate the clock of the output stage, two detect circuits may be used. One circuit detects metastability and another circuit detects metastability resolved to a wrong logic level. The results from one or both detector circuits are used to gate the next clock cycle if needed, waiting for the metastable situation to be resolved.

First claim

What is claimed is:

1. A method comprising:
storing input data in a first data storage circuit responsive to a data sample signal and supplying first data storage output signal;
determining existence of a metastable condition;
responsive to determining the existence of the metastable condition, disabling a clock signal supplied to a second data storage circuit coupled to receive a stored version of the input data;
delaying the data sample signal and generating a delayed data sample signal;
storing the input data in a third data storage circuit responsive to the delayed data sample signal and supplying a third data storage output signal;
wherein determining the existence of a metastable condition includes,
supplying the first data storage output data to a first circuit having a first voltage threshold and generating a first circuit output signal;
supplying the first data storage output signal to a second circuit having a second voltage threshold different than the first voltage threshold and generating a second circuit output signal;
logically comparing the first circuit output signal and the second circuit output signal and providing a first compare signal indicative thereof;
supplying the third data storage output signal to a third circuit having the first voltage threshold and generating a third circuit output signal; and
logically comparing the first circuit output signal and the third circuit output signal and providing a second compare signal indicative thereof.

2. The method as recited in claim 1 wherein the stored version of the input data is the first data storage output signal or the third data storage output signal.

3. The method as recited in claim 1 wherein the first circuit is an inverter and the second circuit is an inverter.

4. The method as recited in claim 1 further comprising:
storing the first data storage output signal or the third data storage output signal in the second data storage circuit in accordance with the clock signal and a clock gating signal.

5. The method as recited in claim 4 further comprising:
filtering the clock gating signal to remove an asserted gating signal if the asserted gating signal is asserted for less than a threshold time.

6. The method as recited in claim 1 further comprising:
generating a clock gating signal based, at least in part, on the first and second compare signals, the clock gating signal being set to pass the clock signal to the second data storage circuit responsive to the first compare signal indicating the first circuit output signal and the second circuit output signal are equal and the second compare signal indicating that the first circuit output signal and the third circuit output signal are equal;
setting the clock gating signal to gate off the clock signal to the second data storage circuit responsive to the first compare signal indicating the first circuit output signal and the second circuit output signal are not equal; and
setting the clock gating signal to gate off the clock signal to the second data storage circuit responsive to the second compare signal indicating the first circuit output signal and the third circuit output signal are not equal.

7. A data sampler circuit comprising:
a first data storage circuit responsive to a data sample signal to sample input data and supply a first data storage output data;
a metastable detect circuit to detect a metastable condition; and
an enable circuit configured to disable a clock signal responsive to detection of the metastable condition;
a second data storage circuit coupled to store a stored version of the input data responsive to the clock signal being enabled;
a delay circuit to delay the data sample signal and generate a delayed data sample signal;
a third data storage circuit responsive to the delayed data sample signal to store the input data and supply third data storage output data;
a first circuit having a first voltage threshold coupled to receive the first data storage output data and generate a first circuit output signal;
a second circuit, having a second voltage threshold different than the first voltage threshold, coupled to receive the first data storage output data and generate a second circuit output signal; and
a first compare circuit to logically compare the first circuit output signal and the second circuit output signal and supply a first compare signal;
a third circuit coupled to receive the third data storage output data and generate a third circuit output signal; and
a second compare circuit is configured to compare the first circuit output signal and the third circuit output signal and supply a second compare signal.

8. The data sampler circuit as recited in claim 7 wherein the first circuit is a first inverter and the second circuit is a second inverter.

9. The data sampler circuit as recited in claim 7 wherein the stored version of the input data is the first data storage output data or the third data storage output data.

10. The data sampler circuit as recited in claim 7 further comprising:
a clock gating circuit coupled to the first compare signal and the second compare signal and configured to assert a clock gating signal to gate off the clock signal responsive to the first compare signal indicating that the first circuit output signal and the second circuit output signal are different and the clock gating circuit is configured to gate off the clock gating signal responsive to the second compare signal indicating that the first circuit output signal and the third circuit output signal are different.

11. The data sampler circuit as recited in claim 10 further comprising:
a filter circuit coupled to the clock gating signal to filter the clock gating signal if the clock gating signal is asserted for less than a threshold time.

12. A data sampler circuit comprising:
a first data storage circuit coupled to receive input data and to receive a data sample signal and is responsive to the data sample signal to sample the input data and supply first data storage output data;
a delay circuit to delay the data sample signal and generate a delayed data sample signal;
a second data storage circuit responsive to the delayed data sample signal to store the input data and supply a second data storage output signal
a metastable detect circuit to detect a metastable condition, the metastable detect circuit including,
a first circuit having a first voltage threshold coupled to receive the first data storage output data and generate a first circuit output signal;
a second circuit, having a second voltage threshold different than the first voltage threshold, coupled to receive the first data storage output data and generate a second circuit output signal;
a compare circuit to logically compare the first circuit output signal and the second circuit output signal and supply a first compare signal;
a third circuit coupled to receive the second data storage output signal and generate a third circuit output signal; and
a second compare circuit configured to compare the first circuit output signal and the third circuit output signal and supply a second compare signal.

Assignees

• Advanced Micro Devices Inc

Inventors

• Sadowski Greg

Classifications

• H03K19/21

  EXCLUSIVE-OR circuits, i.e. giving output if input signal exists at only one input; COINCIDENCE circuits, i.e. giving output only if all input signals are identical · CPC title

• H03K2005/00234

  using circuits having two logic levels · CPC title

• H03K5/1534

  Transition or edge detectors · CPC title

• H03K3/0375 Primary

  provided with means for increasing reliability; for protection; for ensuring a predetermined initial state when the supply voltage has been applied; for storing the actual state when the supply voltage fails (digital storage cells each combining volatile and non-volatile storage properties G11C14/00) · CPC title

• H04L7/0083

  taking measures against momentary loss of synchronisation, e.g. inhibiting the synchronisation, using idle words or using redundant clocks · CPC title