Audio artifact reduction in universal audio jack (UAJ) interface circuits
US-12585423-B2 · Mar 24, 2026 · US
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Kumar Bhoodev patents
Kumar Bhoodev is listed as an inventor on 20 patents in our database. Major assignees and classification codes are summarized below.
| Metric | Value |
|---|---|
| Inventor | Kumar Bhoodev |
| Total patents | 20 |
| First publication | Mar 1, 2016 |
| Latest publication | Mar 24, 2026 |
Notable patents
Publications ranked by popularity score, then publication date.
Apparatus and methods for detecting a microphone condition
US-2026046577-A1 · Feb 12, 2026 · US
Apparatus and methods for detecting a microphone condition
US-12490038-B2 · Dec 2, 2025 · US
Audio artifact reduction in universal audio jack (uaj) interface circuits
US-2025147713-A1 · May 8, 2025 · US
Clock signal transitioning for multi-mode audio processing systems
US-12261611-B2 · Mar 25, 2025 · US
Clock signal transitioning for multi-mode audio processing systems
US-2025023573-A1 · Jan 16, 2025 · US
Apparatus and methods for detecting a microphone condition
US-2023262404-A1 · Aug 17, 2023 · US
Apparatus and methods for detecting a microphone condition
US-11641558-B2 · May 2, 2023 · US
Apparatus and methods for detecting a microphone condition
US-2022070600-A1 · Mar 3, 2022 · US
Highly linear input and output rail-to-rail amplifier
US-11082012-B2 · Aug 3, 2021 · US
Recent patents
Latest publications not already listed above.
Highly linear input and output rail-to-rail amplifier
US-2020358406-A1 · Nov 12, 2020 · US
Microphone bias apparatus and method
US-10674296-B2 · Jun 2, 2020 · US
Synchronous differential signaling protocol
US-10305671-B2 · May 28, 2019 · US
Microphone bias apparatus and method
US-2019037327-A1 · Jan 31, 2019 · US
Synchronous, internal clock edge alignment for integrated circuit testing
US-10128828-B2 · Nov 13, 2018 · US
Synchronous, internal clock edge alignment for integrated circuit testing
US-2017310315-A1 · Oct 26, 2017 · US
Multi-bit pulsed latch cell for use in an integrated circuit
US-9633156-B1 · Apr 25, 2017 · US
Synchronous differential signaling protocol
US-2016344536-A1 · Nov 24, 2016 · US
Multi-bit pulsed latch cell for use in an integrated circuit
US-9300275-B1 · Mar 29, 2016 · US
Noise management method and circuit for asynchronous signals
US-9276594-B2 · Mar 1, 2016 · US
Major assignees
Companies most often associated with this inventor's publications.
| Assignee | Patents |
|---|---|
| Cirrus Logic Int Semiconductor Ltd | 17 |
| Cirrus Logic Inc | 11 |
Top CPC classifications
Most common classification codes across this inventor's patents.
| CPC | Patents |
|---|---|
| H04R29/004 | 5 |
| G06F30/327 | 2 |
| G01R31/318541 | 2 |
| H03K3/012 | 2 |
| G06F17/505 | 2 |