Electronic devices comprising N-type and P-type superlattices

Patent metadata

Field	Value
Publication number	US-10128404-B2
Application number	US-201715594015-A
Country	US
Kind code	B2
Filing date	May 12, 2017
Priority date	May 27, 2014
Publication date	Nov 13, 2018
Grant date	Nov 13, 2018

Abstract

A superlattice and method for forming that superlattice are disclosed. In particular, an engineered layered single crystal structure forming a superlattice is disclosed. The superlattice provides p-type or n-type conductivity, and comprises alternating host layers and impurity layers, wherein: the host layers consist essentially of a semiconductor material; and the impurity layers consist of a donor or acceptor material.

First claim

What is claimed is:

1. A method of making a p-type or n-type superlattice via a film formation process, the method comprising the steps of:
a. loading a substrate into a reaction chamber;
b. heating the substrate to a film formation temperature;
c. forming on the substrate a host layer consisting essentially of a semiconductor material;
d. forming above the host layer an impurity layer consisting of a monolayer of donor or acceptor atoms;
e. forming above the impurity layer another host layer consisting essentially of the semiconductor material;
f. repeating steps (d) to (e) until the superlattice reaches a desired thickness or comprises a desired number of layers;
g. before step (d), forming a first nitrogen terminated surface on the host layer; and
h. before step (e), forming a second nitrogen terminated surface on the impurity layer;
wherein:
step (d) further comprises forming the impurity layer on the first nitrogen terminated surface;
step (e) further comprises forming the other host layer on the second nitrogen terminated surface; and
the host layers consist essentially of a group III metal nitride semiconductor material.

2. The method of claim 1 wherein the semiconductor material is selected from at least one of:
aluminium nitride (AlN);
aluminium gallium nitride (Al x Ga 1−x N) where 0<x<1;
aluminium indium nitride (Al x In 1−x N) where 0<x<1; and
aluminium gallium indium nitride (Al x Ga y In 1−x−y N) where 0<x<1, 0<y<1 and x+y<1.

3. The method of claim 1 wherein the donor atoms are silicon (Si).

4. The method of claim 1 wherein the donor atoms are germanium (Ge).

5. The method of claim 1 wherein the acceptor atoms are magnesium (Mg).

6. The method of claim 1 wherein the acceptor atoms are selected from at least one of:
zinc (Zn); and
carbon (C).

7. The method of claim 1 wherein:
the repeating of steps (d) to (e) is conducted until the superlattice reaches the desired number of layers; and
the desired number of layers is at least 10 host layers and at least 10 impurity layers.

8. The method of claim 1 wherein the film formation process is a vacuum deposition process, a molecular beam epitaxy process or a vapour phase deposition process.

9. The method of claim 1 wherein the film formation temperature is between about 500 ° C. and about 850 ° C.

10. The method of claim 1 wherein the desired thickness is between about 50 nm and about 5 μm.

11. The method of claim 1 wherein the reaction chamber is sufficiently deficient of hydrogen (H), oxygen (O) and carbon (C) species so as to not impact the electronic or structural quality of the superlattice.

12. The method of claim 1 comprising growth interruptions for nitrogen terminated surface preparation using excited molecular nitrogen species.

13. The method of claim 1 wherein the host layers and the impurity layers have a substantially metal polar polarity along a growth direction or a nitrogen polarity along the growth direction.

14. A method of making an electronic device comprising an n-type superlattice providing n-type conductivity and a p-type superlattice providing p-type conductivity, the method comprising the steps of:
a. for the n-type superlattice, forming on a substrate a first host layer consisting essentially of a group III metal nitride semiconductor material;
b. forming above the first host layer a donor impurity layer consisting of a monolayer of donor atoms;
c. forming above the donor impurity layer a second host layer consisting essentially of the group III metal nitride semiconductor material;
d. repeating steps (b) to (c) until the n-type superlattice reaches a desired thickness or comprises a desired number of alternating host layers and donor impurity layers;
e. for the p-type superlattice, forming above the n-type superlattice a third host layer consisting essentially of the group III metal nitride semiconductor material;
f. forming above the third host layer an acceptor impurity layer consisting of a monolayer of acceptor atoms;
g. forming above the acceptor impurity layer a fourth host layer consisting essentially of the group III metal nitride semiconductor material; and
h. repeating steps (f) to (g) until the p-type superlattice reaches a desired thickness or comprises a desired number of alternating host layers and acceptor impurity layers;
wherein the group III metal in the group III metal nitride semiconductor material comprises at least about 50% Al by mol.

15. The method of claim 14 wherein the electronic device is an ultraviolet light emitting diode or an ultraviolet light detector.

16. The method of claim 14 further comprising:
between steps (d) and (e), forming an intrinsic region comprised of one or more group III metal nitride semiconductor materials, wherein the n-type superlattice, the intrinsic region, and the p-type superlattice form a PIN junction.

17. The method of claim 16 wherein the intrinsic region has a bandgap that varies along a growth direction.

18. The method of claim 14 wherein each host layer has a thickness between about 1 nm and about 25 nm.

Assignees

• Silanna UV Technologies Pte Ltd

Inventors

• Atanackovic Petar

Classifications

• Y02E10/50

  Photovoltaic [PV] energy · CPC title

• H01L31/03042

  Electricity · mapped topic

• H01L31/03048

  Electricity · mapped topic

• H01L33/06

  Electricity · mapped topic

• H01L33/12

  Electricity · mapped topic