Ohmic contact to semiconductor

Patent metadata

Field	Value
Publication number	US-9269788-B2
Application number	US-201313775038-A
Country	US
Kind code	B2
Filing date	Feb 22, 2013
Priority date	Feb 23, 2012
Publication date	Feb 23, 2016
Grant date	Feb 23, 2016

Abstract

A solution for forming an ohmic contact to a semiconductor layer is provided. A masking material is applied to a set of contact regions on the surface of the semiconductor layer. Subsequently, one or more layers of a device heterostructure are formed on the non-masked region(s) of the semiconductor layer. The ohmic contact can be formed after the one or more layers of the device heterostructure are formed. The ohmic contact formation can be performed at a processing temperature lower than a temperature range within which a quality of a material forming any semiconductor layer in the device heterostructure is damaged.

First claim

What is claimed is:

1. A method comprising:
forming a device heterostructure including an ohmic contact to a semiconductor layer in a set of semiconductor layers of the device heterostructure without etching the semiconductor layer, wherein the forming includes:
applying a masking material on a set of contact regions corresponding to the ohmic contact on a surface of the semiconductor layer;
forming a protruded region over a set of unmasked regions of the surface of the semiconductor layer after the applying;
forming a set of highly conductive semiconducting layers on the set of contact regions; and
forming the ohmic contact on the set of highly conductive semiconducting layers after formation of the protruded region, wherein the forming the ohmic contact is performed at a processing temperature lower than a temperature range within which a quality of a material forming any one of the set of semiconductor layers in the device heterostructure is damaged.

2. The method of claim 1 , further comprising forming at least one additional semiconductor layer on the protruded region prior to the forming the ohmic contact.

3. The method of claim 1 , further comprising removing the masking material from each of the set of contact regions prior to the forming the set of highly conductive semiconducting layers.

4. The method of claim 1 , further comprising applying a second masking material to a surface of the device heterostructure corresponding to the set of unmasked regions prior to the forming the set of highly conductive semiconducting layers.

5. The method of claim 1 , wherein the set of highly conductive semiconducting layers are formed of group III nitride materials.

6. The method of claim 1 , wherein the set of highly conductive semiconducting layers are lattice matched with the semiconductor layer at an interface of the semiconductor layer and the set of highly conductive semiconducting layers.

7. The method of claim 1 , wherein the forming the set of highly conductive semiconducting layers includes delta doping the set of highly conductive semiconducting layers.

8. The method of claim 1 , wherein the forming the set of highly conductive semiconducting layers includes grading a molar fraction of at least one element of a material forming the set of highly conductive semiconducting layers with respect to a distance from the set of contact regions.

9. The method of claim 8 , wherein the grading is configured to avoid inducing an accumulation of opposite carriers at the set of contact regions.

10. The method of claim 1 , wherein the set of semiconductor layers of the device heterostructure are formed of group III nitride materials.

11. A system comprising:
a fabrication system for forming a device heterostructure including an ohmic contact to a semiconductor layer in a set of semiconductor layers of the device heterostructure without etching the semiconductor layer, wherein the forming includes:
applying a masking material on a set of contact regions corresponding to the ohmic contact on a surface of the semiconductor layer;
forming a protruded region over a set of unmasked regions of the surface of the semiconductor layer after the applying;
forming a set of highly conductive semiconducting layers on the set of contact regions; and
forming the ohmic contact on the set of highly conductive semiconducting layers after formation of the protruded region, wherein the forming the ohmic contact is performed at a processing temperature lower than a temperature range within which a quality of a material forming any one of the set of semiconductor layers in the device heterostructure is damaged.

12. The system of claim 11 , wherein the forming the device heterostructure further includes forming at least one additional semiconductor layer on the protruded region prior to the forming the ohmic contact.

13. The system of claim 11 , wherein the set of highly conductive semiconducting layers are lattice matched with the semiconductor layer at an interface of the semiconductor layer and the set of highly conductive semiconducting layers.

14. The system of claim 11 , wherein the forming the set of highly conductive semiconducting layers includes grading a molar fraction of at least one element of a material forming the set of highly conductive semiconducting layers with respect to a distance from the set of contact regions.

Assignees

• Sensor Electronic Tech Inc

Inventors

• Gaska Remigijus
• Shur Michael
• Yang Jinwei
• Dobrinsky Alexander
• Shatalov Maxim S

Classifications

• H10D64/0116 Primary

  to Group III-V semiconductors · CPC title

• H10H20/816

  having carrier transport control structures, e.g. highly-doped semiconductor layers or current-blocking structures · CPC title

• H10H20/0137

  the light-emitting regions comprising nitride materials · CPC title

• H10H20/81

  Bodies · CPC title

• H10H20/832 Primary

  characterised by their material · CPC title