Ultraviolet reflective rough adhesive contact

Patent metadata

Field	Value
Publication number	US-9287449-B2
Application number	US-201414150949-A
Country	US
Kind code	B2
Filing date	Jan 9, 2014
Priority date	Jan 9, 2013
Publication date	Mar 15, 2016
Grant date	Mar 15, 2016

Abstract

A device including a first semiconductor layer and a contact to the first semiconductor layer is disclosed. An interface between the first semiconductor layer and the contact includes a first roughness profile having a characteristic height and a characteristic width. The characteristic height can correspond to an average vertical distance between crests and adjacent valleys in the first roughness profile. The characteristic width can correspond to an average lateral distance between the crests and adjacent valleys in the first roughness profile.

First claim

What is claimed is:

1. A device comprising:
a first semiconductor layer;
a contact to the first semiconductor layer, wherein an interface between the first semiconductor layer and the contact includes a first roughness profile having a characteristic height of at least three nanometers and a characteristic width of at least 0.1 micron; and
an interlayer located between the first semiconductor layer and the contact, wherein the interlayer comprises a plurality of islands each having a closed boundary that is separate from the first semiconductor layer and the contact, wherein some of the plurality of islands have a boundary that extends into both the first semiconductor layer and the contact.

2. The device of claim 1 , wherein the characteristic height is an average vertical distance between adjacent crests and valleys of the first roughness profile.

3. The device of claim 1 , wherein the characteristic width is an average lateral distance between adjacent crests and valleys of the first roughness profile.

4. The device of claim 3 , the interface between the contact and the first semiconductor layer further including a second roughness profile, wherein a characteristic width of the second roughness profile is at least five times smaller than the characteristic width of the first roughness profile.

5. The device of claim 1 , the interface between the contact and the first semiconductor layer further including a second roughness profile, wherein the first roughness profile is configured based on adhesion of the contact to the first semiconductor layer and the second roughness profile is configured based on current spreading in the first semiconductor layer.

6. The device of claim 1 , wherein the plurality of islands includes islands formed of at least one of: a metal, an oxide, a nitride, or graphene.

7. The device of claim 6 , wherein a thickness of the interlayer is less than the characteristic height of the first roughness profile.

8. The device of claim 1 , further comprising a second semiconductor layer located between the first semiconductor layer and the contact, wherein the second semiconductor layer is configured to improve an ohmic contact between the first semiconductor layer and the contact.

9. The device of claim 8 , wherein the second semiconductor is laterally inhomogeneous and comprises a first plurality of regions of a first type and a second plurality of regions of a second type, wherein the first type includes a first material having a high conductivity that includes a total voltage drop of less than twenty percent of a total operational voltage of the device, and the second type includes a second material transparent to radiation of a target wavelength.

10. The device of claim 1 , the contact including a plurality of sublayers, wherein each sublayer includes a metal distinct from a metal of the other sublayers.

11. A device comprising:
a first semiconductor layer;
a contact to the first semiconductor layer, wherein an interface between the first semiconductor layer and the contact includes a first roughness profile with a characteristic height and a characteristic width, wherein the characteristic height is an average vertical distance between adjacent crests and valleys of the first roughness profile, and is at least approximately three nanometers, and wherein the characteristic width is an average lateral distance between adjacent crests and valleys of the first roughness profile, and is within a range of approximately 0.1 micron to approximately fifty microns; and
an interlayer located between the first semiconductor layer and the contact, wherein the interlayer comprises a plurality of islands each having a closed boundary that is separate from the first semiconductor layer and the contact, wherein some of the plurality of islands have a boundary that extends into both the first semiconductor layer and the contact.

12. The device of claim 11 , the interface between the contact and the first semiconductor layer further including a second roughness profile, wherein a characteristic width of the second roughness profile is at least five times smaller than the characteristic width of the first roughness profile.

13. The device of claim 11 , the interface between the contact and the first semiconductor layer further including a second roughness profile, wherein the first roughness profile is configured based on adhesion of the contact to the first semiconductor layer and the second roughness profile is configured based on current spreading in the first semiconductor layer.

14. The device of claim 11 , wherein the plurality of islands includes islands formed of at least one of: a metal, an oxide, a nitride, or graphene.

15. The device of claim 14 , wherein a thickness of the interlayer is less than the characteristic height of the first roughness profile.

16. The device of claim 11 , further comprising a second semiconductor layer located between the first semiconductor layer and the contact, wherein the second semiconductor layer is configured to improve an ohmic contact between the first semiconductor layer and the contact.

17. The device of claim 16 , wherein the second semiconductor layer is laterally inhomogeneous and comprises a plurality of regions of a first type and a second type, the first type including a material having a high conductivity that includes a total voltage drop of less than twenty percent of a total operational voltage of the device, and the second type including a material being transparent to radiation of a target wavelength.

18. The device of claim 11 , the contact including a plurality of sublayers, wherein each sublayer includes a metal distinct from a metal of the other sublayers.

19. A method comprising:
fabricating a device, the device comprising:
a first semiconductor layer;
a contact to the first semiconductor layer, wherein an interface between the first semiconductor layer and the contact includes a first roughness profile having a characteristic height of at least three nanometers and a characteristic width of at least 0.1 micron; and
an interlayer located between the first semiconductor layer and the contact, wherein the interlayer comprises a plurality of islands each having a closed boundary that is separate from the first semiconductor layer and the contact, wherein some of the plurality of islands have a boundary that extends into both the first semiconductor layer and the contact.

20. The method of claim 19 , wherein the fabricating includes:
depositing an interlayer over the first semiconductor layer;
patterning the interlayer;
depositing a metallic layer over the interlayer;
etching at least one of: the interlayer or the semiconductor layer using the metallic layer as a mask; and
depositing a reflective material into the etched regions.

21. The method of claim 20 , wherein the metallic layer and the reflective material form at least a portion of the contact.

22. The method of claim 19 , wherein the fabricating includes depositing a second semiconductor layer over the first semiconductor layer, wherein the second semiconductor layer is located between the contact and the first semiconductor layer.

23. The device of claim 1 , wherein some of the plurality of islands have boundary portions that are in contact with boundary portions of adjacent islands.

Assignees

• Sensor Electronic Tech Inc

Inventors

• Gaska Remigijus
• Shatalov Maxim S
• Lunev Alexander
• Dobrinsky Alexander
• Yang Jinwei
• Shur Michael

Classifications

• H10W72/01225

  in solid form, e.g. by using a powder or by stud bumping · CPC title

• H10W72/944

  Dispositions of multiple bond pads · CPC title

• H10W72/90

  Bond pads, in general · CPC title

• H10W72/29

  Bond pads specially adapted therefor · CPC title

• H10W72/20

  Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps · CPC title