Multi-height FinFETs with coplanar topography background

Patent metadata

Field	Value
Publication number	US-9331201-B2
Application number	US-201313906428-A
Country	US
Kind code	B2
Filing date	May 31, 2013
Priority date	May 31, 2013
Publication date	May 3, 2016
Grant date	May 3, 2016

Abstract

A semiconductor structure is provided that has semiconductor fins having variable heights without any undue topography. The semiconductor structure includes a semiconductor substrate having a first semiconductor surface and a second semiconductor surface, wherein the first semiconductor surface is vertically offset and located above the second semiconductor surface. An oxide region is located directly on the first semiconductor surface and/or the second semiconductor surface. A first set of first semiconductor fins having a first height is located above the first semiconductor surface of the semiconductor substrate. A second set of second semiconductor fins having a second height is located above the second semiconductor surface, wherein the second height is different than the first height and wherein each first semiconductor fin and each second semiconductor fin have topmost surfaces which are coplanar with each other.

First claim

The invention claimed is:

1. A semiconductor structure comprising:
a semiconductor substrate comprising a first semiconductor surface and a second semiconductor surface, wherein said first semiconductor surface is vertically offset and located above said second semiconductor surface;
an oxide region located directly on at least one of the first semiconductor surface and the second semiconductor surface;
a first set of first semiconductor fins having a first height and located above said first semiconductor surface of the semiconductor substrate; and
a second set of second semiconductor fins having a second height and located above the second semiconductor surface, wherein the second height is different than the first height and each first semiconductor fin and each second semiconductor fin has a topmost surface, and the topmost surfaces of the first and second semiconductor fins are coplanar with each other, and further wherein one vertical sidewall surface of each first semiconductor fin and each second semiconductor fin that is present on said oxide region is vertically aligned to an outermost vertical edge of said oxide region.

2. The semiconductor structure of claim 1 , wherein said oxide region is only located directly on said first semiconductor surface of the semiconductor substrate.

3. The semiconductor structure of claim 1 , wherein said oxide region is only located directly on said second semiconductor surface of the semiconductor substrate.

4. The semiconductor structure of claim 1 , wherein said oxide region is located directly on both said first semiconductor surface and the second semiconductor surface.

5. The semiconductor structure of claim 1 , wherein an insulator layer is located on a portion of the first semiconductor surface not including said first set of first semiconductor fins.

6. The semiconductor structure of claim 1 , wherein each semiconductor fin of the first and second sets is comprised of silicon.

7. The semiconductor structure of claim 1 , further comprising a gate structure straddling each first semiconductor fin and each second semiconductor fin.

8. The semiconductor structure of claim 7 , wherein said gate structure includes a gate dielectric and a gate conductor.

9. The semiconductor structure of claim 8 , wherein said gate dielectric is present on each vertical sidewall surface and the topmost surface of each of said first and second semiconductor fins.

10. The semiconductor structure of claim 1 , wherein said semiconductor substrate comprises a bulk semiconductor material.

11. A semiconductor structure comprising:
a bulk semiconductor substrate comprising a first semiconductor surface and a second semiconductor surface, wherein said first semiconductor surface is vertically offset and located above said second semiconductor surface;
a first oxide region located directly on the first semiconductor surface;
a second oxide region located directly on the second semiconductor surface, wherein the first oxide region has a topmost surface that is vertically offset and located above a topmost surface of the second oxide region;
a first set of first semiconductor fins having a first height and located directly on the topmost surface of said first oxide region; and
a second set of second semiconductor fins having a second height and located directly on the topmost surface of the second oxide region, wherein the second height is greater than the first height and each first semiconductor fin and each second semiconductor fin has a topmost surface, and the topmost surfaces of the first and second semiconductor fins are coplanar with each other, and further wherein one vertical sidewall surface of each first semiconductor fin is vertically aligned to an outermost vertical edge of said first oxide region and one vertical sidewall surface of each second semiconductor fin is vertically aligned to an outermost vertical edge of said second oxide region.

12. The semiconductor structure of claim 11 , wherein an insulator layer is located on a portion of the first semiconductor surface not including said first set of first semiconductor fins.

13. The semiconductor structure of claim 11 , wherein each semiconductor fin of the first and second sets is comprised of silicon.

14. The semiconductor structure of claim 11 , further comprising a gate structure straddling each first semiconductor fin and each second semiconductor fin.

15. The semiconductor structure of claim 14 , wherein said gate structure includes a gate dielectric and a gate conductor.

16. The semiconductor structure of claim 15 , wherein said gate dielectric is present on each vertical sidewall surface and the topmost surface of each of said first and second semiconductor fins.

17. The semiconductor structure of claim 12 wherein a topmost surface of said insulator layer is coplanar with a topmost surface of said second oxide structure.

Assignees

• Globalfoundries Inc

Inventors

• Cheng Kangguo
• Doris Bruce B
• Hashemi Pouya
• Khakifirooz Ali
• Reznicek Alexander

Classifications

• H10D30/024

  of fin field-effect transistors [FinFET] · CPC title

• H10D30/62 Primary

  Fin field-effect transistors [FinFET] · CPC title

• H10D87/00

  Integrated devices comprising both bulk components and either SOI or SOS components on the same substrate · CPC title

• H10D86/215

  comprising FinFETs · CPC title

• H10D86/011

  comprising FinFETs · CPC title