FinFET including varied fin height

Patent metadata

Field	Value
Publication number	US-9362178-B1
Application number	US-201514745736-A
Country	US
Kind code	B1
Filing date	Jun 22, 2015
Priority date	Mar 31, 2015
Publication date	Jun 7, 2016
Grant date	Jun 7, 2016

Abstract

According to another embodiment, a semiconductor finFET device includes a semiconductor substrate. The finFET device further includes at least one first semiconductor fin on the semiconductor substrate. The first semiconductor fin comprises a first semiconductor portion extending to a first fin top to define a first height, and a first insulator portion interposed between the first semiconductor portion and the semiconductor substrate. A second semiconductor fin on the semiconductor substrate has a second semiconductor portion extending to a second fin top to define a second height, and a second insulator portion interposed between the second semiconductor portion and the semiconductor substrate, the second height being different from the first height.

First claim

What is claimed is:

1. A method of fabricating a finFET semiconductor device, the method comprising:
forming a plurality of semiconductor fins on a semiconductor substrate, at least one first semiconductor fin among the plurality of semiconductor fins including a first lower semiconductor portion and a first upper semiconductor portion, and at least one second semiconductor fin including a second lower semiconductor portion and a second upper semiconductor portion;
etching the first lower semiconductor portion to form a first cavity having a first cavity height extending between the semiconductor substrate and a first upper semiconductor portion, and etching the second lower semiconductor portion to form a second cavity height extending between the semiconductor substrate and a second upper semiconductor portion, the second cavity height being different from the first cavity height; and
filling the first cavity and the second cavity with an insulator material such that a first height of the first upper semiconductor portion is different than a second height of the second upper semiconductor portion.

2. The method of claim 1 , wherein a combination of the insulator material and the first upper semiconductor portion defines a first total height of the at least one first semiconductor fin, and a combination of the insulator material and the second upper semiconductor portion defines a second total height of the at least one second semiconductor fin.

3. The method of claim 2 , wherein the first total height is substantially equal to the second total height such that a first top of the at least one first semiconductor fin is at a same level as a second top of the at least one second semiconductor fin.

4. The method of claim 3 , wherein etching the first cavity comprises selectively etching the first and second lower semiconductor portions with respect to the first and second upper semiconductor portions, respectively, such that the first and second upper semiconductor portions are suspended over the semiconductor substrate.

5. The method of claim 4 , wherein forming the plurality of semiconductor fins comprises:
forming a first semiconductor layer comprising a first semiconductor material on an upper surface of a bulk substrate layer of the semiconductor substrate;
forming a second semiconductor layer comprising a second semiconductor material on an upper surface of the first semiconductor layer, the second semiconductor material being different from the first semiconductor material; and
patterning the semiconductor substrate to form the plurality of semiconductor fins such that the first and second lower semiconductor portions comprise the first semiconductor material and the first and second upper semiconductor portions comprise the second semiconductor material.

6. The method of claim 5 , wherein forming the plurality of semiconductor fins further comprises prior to patterning the semiconductor substrate, etching a first region of the first semiconductor layer and the second semiconductor layer with respect to a second region of the first semiconductor layer and the second semiconductor layer, and forming in the etched second region a third semiconductor material having an upper surface that is flush with an upper surface of the second semiconductor layer of the first region.

7. The method of claim 6 , wherein the first semiconductor layer is epitaxial grown from the upper surface of the semiconductor material, and the second semiconductor layer is epitaxially grown from the upper surface of the first semiconductor layer.

8. The method of claim 7 , wherein the third semiconductor layer is epitaxially grown from the first semiconductor layer of the first region, and the sidewalls of the first and second semiconductor layers of the second region.

9. The method of claim 8 , wherein selectively etching the first and second lower semiconductor portions includes performing a reactive ion etch on the at least one first and second semiconductor fins that is selective to the second and third semiconductor materials.

10. The method of claim 9 , wherein the first semiconductor material is silicon germanium (SiGe), the second semiconductor material is silicon (Si), and the third semiconductor material is one of Si or SiGe having a percentage of germanium (Ge) that is less than a percentage of Ge of the first semiconductor material.

11. The method of claim 10 , wherein the insulator material is silicon dioxide (SiO 2 ).

12. The method of claim 11 further comprising forming a gate stack on the semiconductor substrate prior to etching the first and second cavities, the gate stack wrapping completely around the outer surfaces of the plurality of semiconductor fins.

13. The method of claim 12 , wherein the first and second cavities are etched after forming the gate stack such that a remaining portion of the gate stack anchors the suspended first and second upper semiconductor portions.

Assignees

• IBM

Inventors

• Cao Qing
• Cheng Kangguo
• Li Zhengwen
• Liu Fei

Classifications

• H10P50/242

  of Group IV materials · CPC title

• H10P14/3411

  Silicon, silicon germanium or germanium · CPC title

• H10D86/215

  comprising FinFETs · CPC title

• H10D86/011 Primary

  comprising FinFETs · CPC title

• H10D84/0193

  the components including FinFETs · CPC title