Methods of forming different FinFET devices having different fin heights and an integrated circuit product containing such devices

Patent metadata

Field	Value
Publication number	US-9530775-B2
Application number	US-201313916013-A
Country	US
Kind code	B2
Filing date	Jun 12, 2013
Priority date	Jun 12, 2013
Publication date	Dec 27, 2016
Grant date	Dec 27, 2016

Abstract

One illustrative method disclosed herein includes forming a plurality of trenches in a plurality of active regions of a substrate that defines at least a first plurality of fins and a second plurality of fins for first and second FinFET devices, respectively, forming liner materials adjacent to the first and second plurality of fins, wherein the liner materials adjacent the first fins and the second fins have a different thickness. The method also includes removing insulating material to expose portions of the liner materials, performing an etching process to remove portions of the liner materials so as to expose at least one fin in the first plurality of fins to a first height and at least one of the second plurality of fins to a second height that is different from the first height.

First claim

What is claimed:

1. A method of forming an integrated circuit product, comprising:
forming a patterned hard mask layer above a semiconductor substrate;
performing at least one first etching process through said patterned hard mask layer to form a plurality of trenches in said semiconductor substrate that define a first fin above a first active region of said substrate and a second fin above a second active region of said substrate;
forming liner material adjacent to at least said first fin to a first thickness;
forming liner material adjacent to at least said second fin to a second thickness that is different from said first thickness;
forming a layer of insulating material in said trenches adjacent said liner materials and above said patterned hard mask layer;
performing at least one process operation to remove portions of said layer of insulating material and to expose portions of said liner materials;
performing at least one second etching process to remove portions of said liner materials and said patterned hard mask layer, wherein removal of said liner materials results in exposing said first fin to a first height and said second fin to a second height that is different from said first height; and
performing at least one third etching process on said layer of insulating material to thereby define a reduced-thickness layer of insulating material.

2. A method of forming a FinFET device, comprising:
forming a patterned hard mask layer above a semiconductor substrate;
performing at least one first etching process through said patterned hard mask layer to form a plurality of trenches in said semiconductor substrate that define a first plurality of fins above a first active region of said substrate and a second plurality of fins above a second active region of said substrate;
forming a first liner layer in said plurality of trenches, above said hard mask and adjacent to at least said first and second plurality of fins;
performing a second etching process to remove at least portions of said first liner layer positioned adjacent said second plurality of fins;
forming a second liner layer above said first liner layer and adjacent to said second plurality of fins;
forming a layer of insulating material in said trenches above said first and second liner layers and above said patterned hard mask layer;
performing a process operation to remove portions of said layer of insulating material and to expose portions of at least said second liner layer;
performing at least one third etching process to remove portions of said first and second liner layers and said patterned hard mask layer, wherein removal of portions of said first and second liner layers results in exposing at least one of said first plurality of fins to a first height and exposing at least one of said second plurality of fins to a second height that is less than said first height; and
performing at least one fourth etching process on said layer of insulating material to thereby define a reduced-thickness layer of insulating material.

3. The method of claim 2 , wherein said first plurality of fins are for a first FinFET device of a first type and said second plurality of fins are for a second FinFET device of a second type that is opposite to said first type.

4. The method of claim 2 , wherein said first plurality of fins are for a first FinFET device and said second plurality of fins are for a second FinFET device and wherein said first FinFET device and said second FinFET device are of a same type.

5. The method of claim 2 , further comprising:
forming a first gate structure around said first plurality of fins; and
forming a second gate structure around said second plurality of fins.

6. The method of claim 2 , wherein said first and second liner layers have the same approximate thickness.

7. The method of claim 2 , wherein said first and second liner layers are made of the same material.

8. A method of forming an integrated circuit product, comprising:
forming a patterned hard mask layer above a semiconductor substrate;
performing at least one first etching process through said patterned hard mask layer to form a plurality of trenches in said semiconductor substrate that define a first plurality of fins above a first active region of said substrate and a second plurality of fins above a second active region of said substrate;
forming liner material adjacent to at least said first plurality of fins to a first thickness;
forming liner material adjacent to at least said second plurality of fins to a second thickness that is different from said first thickness;
forming a layer of insulating material in said trenches adjacent said liner materials and above said patterned hard mask layer;
performing at least one process operation to remove portions of said layer of insulating material and to expose portions of said liner materials;
performing at least one second etching process to remove portions of said liner materials and said patterned hard mask layer, wherein removal of said liner materials results in exposing at least one of said first plurality of fins to a first height and at least one of said second plurality of fins to a second height that is different from said first height; and
performing at least one third etching process on said layer of insulating material to thereby define a reduced-thickness layer of insulating material.

9. The method of claim 8 , wherein said first plurality of fins are for a first FinFET device of a first type and said second plurality of fins are for a second FinFET device of a second type that is opposite to said first type.

10. The method of claim 8 , wherein said first plurality of fins are for a first FinFET device and said second plurality of fins are for a second FinFET device and wherein said first FinFET device and said second FinFET device are of a same type.

11. The method of claim 8 , further comprising:
forming a first gate structure around said first plurality of fins; and
forming a second gate structure around said second plurality of fins.

12. The method of claim 8 , wherein said patterned hard mask layer is comprised of silicon nitride, said liner material is comprised of aluminum oxide and said layer of insulating material is comprised of silicon dioxide.

13. The method of claim 8 , wherein performing said process operation comprises performing a chemical mechanical polishing process operation.

14. The method of claim 8 , wherein said first thickness is greater than said second thickness and said first height is greater than said second height.

15. The method of claim 8 , wherein said first thickness is less than said second thickness and said first height is less than said second height.

16. The method of claim 8 , wherein said liner material positioned adjacent said first plurality of fins comprises multiple layers of liner material, said liner material positioned adjacent said second plurality of fins comprises a single layer of liner material, said first thickness is greater than said second thickness and said first height is greater than said second height.

17. The method of claim 8 , wherein said liner material positioned adjacent said first plurality of fins comprises a single layer of liner material, said liner material positioned adjacent said second plurality of fins comprises a single layer of liner material, said first thickness is greater than said second thickness and said first height is greater than said second height.

18. The method of claim 8 , wherein said liner materials are made of the same material.

Assignees

• Globalfoundries Inc
• IBM

Inventors

• Cai Xiuyu
• Xie Ruilong
• Cheng Kangguo
• Khakifirooz Ali

Classifications

• H10D84/0193

  the components including FinFETs · CPC title

• H10D84/0188

  Manufacturing their isolation regions · CPC title

• H10D84/0158

  the components including FinFETs · CPC title

• H10D84/0151

  Manufacturing their isolation regions · CPC title

• H10D84/038

  using silicon technology, e.g. SiGe · CPC title