Methods of generating integrated circuit layout using standard cell library

Patent metadata

Field	Value
Publication number	US-10108772-B2
Application number	US-201615271883-A
Country	US
Kind code	B2
Filing date	Sep 21, 2016
Priority date	Aug 22, 2014
Publication date	Oct 23, 2018
Grant date	Oct 23, 2018

Abstract

Methods of generating an integrated circuit layout include forming a standard cell by providing a first active area adjacent to a first cell boundary line. The first active area is spaced apart from the first cell boundary line by a first distance. A second active area is provided adjacent to a second cell boundary line. The second cell boundary line opposes the first cell boundary line. The second active area is spaced apart from the second cell boundary line by a second distance. Fins are formed on the first and second active areas. The fins extend in a first direction and parallel to one another in a second direction substantially perpendicular to the first direction. The first cell boundary line is parallel to the fins. The first distance and the second distance remain constant when a number of the fins on the first and second active areas is changed.

First claim

What is claimed is:

1. An integrated circuit (IC), comprising:
at least one standard cell including,
a plurality of fins extending in a first direction and parallel to one another in a second direction substantially perpendicular to the first direction,
a first active area adjacent to a first cell boundary line, the first cell boundary line being parallel to the plurality of fins, and the first active area being spaced apart from the first cell boundary line by a first distance, and
a second active area adjacent to a second cell boundary line, the second cell boundary line opposing the first cell boundary line, and the second active area being spaced apart from the second cell boundary line by a second distance, the first distance and the second distance remaining constant,

wherein the plurality of fins include,
active fins on the first and second active areas, and
dummy fins on dummy areas, the first and second active areas not being in the dummy areas, the dummy fins including,
at least one first dummy fin between the first cell boundary line and the first active area,
at least one second dummy fin between the second cell boundary line and the second active area, and
at least one third dummy fin between the first active area and second active area.

2. The IC of claim 1 , wherein a space between the first active area and the second active area decreases as lengths of the first and second active areas in the second direction increase.

3. The IC of claim 1 , wherein the first and second distances remain constant regardless of changes in lengths of the first and second active areas in the second direction.

4. The IC of claim 1 , wherein the first distance is substantially equal to the second distance.

5. The IC of claim 1 , wherein
the at least one standard cell further includes a plurality of conductive lines extending in the second direction, and
the conductive lines are parallel to one another in the first direction.

6. The IC of claim 1 , wherein a conductivity type of the first active area is different from a conductivity type of the second active area.

7. An integrated circuit (IC), comprising:
at least one standard cell including,
a plurality of active fins extending in a first direction and parallel to one another in a second direction substantially perpendicular to the first direction, the plurality of active fins including a first active fin and a second active fin on a first active area and a second active area, respectively, the first active fin being closest to a first cell boundary line and spaced apart from the first cell boundary line by a first distance, the second active fin being closest to a second cell boundary line and spaced apart from the second cell boundary line by a second distance, the first distance and the second distance remaining constant, and
a plurality of dummy fins parallel to the plurality of active fins, the plurality of dummy fins on dummy areas, the plurality of dummy fins including,
at least one first dummy fin between the first cell boundary line and the first active fin,
at least one second dummy fin between the second cell boundary line and the second active fin, and
at least one third dummy fin between the first active area and second active area.

8. The IC of claim 7 , wherein a number of the at least one first dummy fin is equal to a number of the at least one second dummy fin.

9. The IC of claim 7 , wherein a number of the at least one first dummy fin and a number of the at least one second dummy fin remain constant regardless of changes in a number of the plurality of active fins.

Assignees

• Samsung Electronics Co Ltd

Inventors

• Baek Sang-Hoon
• Seo Jae-Woo
• Yang Gi-Young
• Lee Dal-Hee
• Cho Sung-Wee

Classifications

• H10W20/43

  Layouts of interconnections · CPC title

• G06F2111/04

  Constraint-based CAD · CPC title

• G06F30/398

  Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM] (optical proximity correction [OPC] design processes G03F1/36) · CPC title

• G06F30/00

  Computer-aided design [CAD] · CPC title

• G06F2119/06

  Power analysis or power optimisation · CPC title