Fin transistor and semiconductor integrated circuit including the same

Patent metadata

Field	Value
Publication number	US-9299842-B2
Application number	US-201314026345-A
Country	US
Kind code	B2
Filing date	Sep 13, 2013
Priority date	Sep 14, 2012
Publication date	Mar 29, 2016
Grant date	Mar 29, 2016

Abstract

Provided are a fin transistor including a plurality of fins and a semiconductor integrated circuit including a plurality of fin transistors. A width of at least one fin of the plurality of fins is different from widths of the other fins, and each width of the plurality of fins is individually determined based on the electrical characteristics of the fin transistor.

First claim

What is claimed is:

1. A multi-fin transistor comprising:
a plurality of fins; and
a common gate electrode above the plurality of fins,
wherein a width of at least one fin of the plurality of fins is different from widths of the other fins, and each width of the plurality of fins is individually determined based on electrical characteristics of the multi-fin transistor,
wherein the width of the at least one fin is indicated in a design unit by a mark layer to change the width based on the electrical characteristics of the multi-fin transistor
wherein the width of the at least one fin is changed in the design unit according to a new library generated by using the mark layer, and
wherein the mark layer comprises at least one of,
a first mark layer configured to indicate an increase in a width of at least one fin set in a previously designed layout, and
a second mark layer configured to indicate a decrease in the width of the at least one fin set to the previously designed layout.

2. The multi-fin transistor of claim 1 , wherein the first and second mark layers are distinguished from each other in the design unit by using at least one of different colors and different boundaries.

3. A multi-fin transistor comprising:
a plurality of fins; and
a common gate electrode above the plurality of fins,
wherein a width of at least one fin of the plurality of fins is different from widths of the other fins, and each width of the plurality of fins is individually determined based on electrical characteristics of the multi-fin transistor,
wherein the width of the at least one fin is indicated in a design unit by a mark layer to change the width based on the electrical characteristics of the multi-fin transistor, and
wherein a pitch between the plurality of fins is constant even when the width of the at least one fin is changed.

4. The multi-fin transistor of claim 3 , wherein the mark layer comprises at least one of:
a first mark layer configured to indicate the at least one fin; and
a second mark layer configured to indicate the multi-fin transistor including the at least one fin.

5. The multi-fin transistor of claim 3 , wherein the plurality of fins comprise at least one active fin.

6. The multi-fin transistor of claim 3 , wherein the plurality of fins include at least one dummy fin.

7. A multi-fin transistor comprising:
a plurality of fins; and
a common gate electrode above the plurality of fins,
wherein a width of at least one fin of the plurality of fins is different from widths of the other fins, and each width of the plurality of fins is individually determined based on electrical characteristics of the multi-fin transistor, and
wherein when all of the plurality of fins are active fins, a number of the plurality of fins is r, and a number of selectable widths is n (r and n being natural numbers equal to or greater than 2), a number of cases for a total width of the multi-fin transistor is nHr, which is a repeating combination based on the numbers r and n.

8. A multi-fin transistor comprising:
a plurality of fins; and
a common gate electrode above the plurality of fins,
wherein a width of at least one fin of the plurality of fins is different from widths of the other fins, and each width of the plurality of fins is individually determined based on electrical characteristics of the multi-fin transistor, and
wherein when a number of the plurality of fins is r and a number of selectable widths is n (r and n being natural numbers equal to or greater than 2), a number of cases for a total width of the fin transistor is

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 which is a sum of repeating combinations based on the numbers r and n.

9. The multi-fin transistor of claim 3 , wherein the electrical characteristics of the multi-fin transistor are determined based on a set value of a ratio of a rising time to a falling time of the multi-fin transistor.

10. The multi-fin transistor of claim 3 , wherein the electrical characteristics of the multi-fin transistor are determined based on a set value of a ratio of a low-to-high propagation delay time to a high-to-low propagation delay time of the multi-fin transistor.

11. The multi-fin transistor of claim 3 , wherein the each width of the plurality of fins is a width shown in a two-dimensional (2D) layout.

12. A non-transitory computer program product, loadable directly into a memory of an image processing system, comprising:
a tangible computer readable medium including program code segments embedded thereon,
wherein the computer program product is configured to design a library of a multi-fin transistor including a plurality of fins based on layouts, and generate a new library by generating and applying at least one mark layer to a previously-created layout when changing a width of at least one fin of the plurality of fins based on electrical characteristics of the multi-fin transistor.

13. The computer program product of claim 12 , wherein
the width of the at least one fin is indicated in a design unit by a mark layer to change the width based on the electrical characteristics of the multi-fin transistor, and
the width of the at least one fin is changed in the design unit according to a new library generated using the mark layer.

14. The computer program product Of claim 13 , wherein the mark layer comprises at least one of:
a first mark layer configured to indicate an increase in a width of at least one fin set in a previously designed layout; and
a second mark layer configured to indicate a decrease in the width of the at least one fin set to the previously designed layout.

15. The computer program product of claim 14 , wherein the first and second mark layers are distinguished from each other in the design unit by using at least one of different colors and different boundaries.

16. The computer program product of claim 12 , wherein a pitch between the plurality of fins is constant even when the width of the at least one fin is changed.

Assignees

• Samsung Electronics Co Ltd

Inventors

• Baek Sang-Hoon

Classifications

• G06F30/36

  Circuit design at the analogue level · CPC title

• G06F30/398

  Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM] (optical proximity correction [OPC] design processes G03F1/36) · CPC title

• H10D30/62 Primary

  Fin field-effect transistors [FinFET] · CPC title

• H10D30/0243

  using dummy structures having essentially the same shapes as the semiconductor bodies, e.g. to provide stability · CPC title

• H10D84/853

  comprising FinFETs · CPC title