Bridge interconnection with layered interconnect structures

Patent metadata

Field	Value
Publication number	US-10103103-B2
Application number	US-201715478858-A
Country	US
Kind code	B2
Filing date	Apr 4, 2017
Priority date	May 28, 2013
Publication date	Oct 16, 2018
Grant date	Oct 16, 2018

Abstract

Embodiments of the present disclosure are directed towards techniques and configurations for layered interconnect structures for bridge interconnection in integrated circuit assemblies. In one embodiment, an apparatus may include a substrate and a bridge embedded in the substrate. The bridge may be configured to route electrical signals between two dies. An interconnect structure, electrically coupled with the bridge, may include a via structure including a first conductive material, a barrier layer including a second conductive material disposed on the via structure, and a solderable material including a third conductive material disposed on the barrier layer. The first conductive material, the second conductive material, and the third conductive material may have different chemical composition. Other embodiments may be described and/or claimed.

First claim

What is claimed is:

1. An apparatus comprising:
a substrate that includes a patterned metal layer, and a dielectric layer formed over and around the patterned metal layer;
a bridge composed of a glass substrate and mounted inside the substrate on the patterned metal layer with an adhesive layer;
a first die electrically coupled with the bridge; and
a second die electrically coupled with the bridge;
wherein the bridge includes one or more electrical routing features disposed therein, to route electrical signals between the first die and the second die, wherein the electrical routing features include one or more pads disposed on and protruding above a surface of the glass substrate of the bridge and disposed inside the dielectric layer of the substrate.

2. The apparatus of claim 1 , wherein the one or more electrical routing features comprise one or more interconnect structures.

3. The apparatus of claim 2 , wherein the first die or the second die are electrically coupled with the bridge by one of the one or more interconnect structures.

4. The apparatus of claim 2 , wherein an interconnect structure of the one or more interconnect structures includes:
a via structure that includes a first conductive material, wherein the via structure is to route the electrical signals through at least a portion of the substrate;
a barrier layer that includes a second conductive material disposed on the via structure; and
a solderable material that includes a third conductive material disposed on the barrier layer;
wherein the first conductive material, the second conductive material, and the third conductive material have a different chemical composition from one another.

5. The apparatus of claim 4 , wherein the barrier layer covers a surface of the via structure to inhibit diffusion of the first conductive material.

6. The apparatus of claim 4 , wherein first conductive material comprises copper (Cu), the second conductive material comprises nickel (Ni), and the third conductive material comprises tin (Sn).

7. The apparatus of claim 1 , wherein the first die includes a processor and the second die includes a memory die or another processor.

8. The apparatus of claim 1 , wherein the electrical signals are input/output (I/O) signals.

9. The apparatus of claim 1 , wherein the first die or the second die are further physically coupled with a surface of the substrate.

10. The apparatus of claim 1 , wherein the bridge is an element positioned within a bridge cavity of the substrate.

11. A system comprising:
a printed circuit board (PCB); and
a package coupled with the PCB, wherein the package includes:
a substrate that includes a patterned metal layer, and a dielectric layer formed over and around the patterned metal layer;
a bridge composed of a glass substrate and mounted inside the substrate on the patterned metal layer with an adhesive layer;
a first die electrically coupled with a bridge; and
a second die electrically coupled with the bridge;
wherein the bridge includes one or more electrical routing features disposed therein, to route electrical signals between the first die and the second die, wherein the electrical routing features include one or more pads disposed on and protruding above a surface of the substrate of the bridge and disposed inside the dielectric layer of the substrate; and
wherein the bridge glass substrate includes a glass material that is different than a material of the substrate.

12. The system of claim 11 , wherein the one or more electrical routing features comprise one or more interconnect structures.

13. The system of claim 12 , wherein the first die or the second die are electrically coupled with the bridge by one of the one or more interconnect structures.

14. The system of claim 12 , wherein an interconnect structure of the one or more interconnect structures includes:
a via structure that includes a first conductive material, wherein the via structure is to route the electrical signals through at least a portion of the substrate;
a barrier layer that includes a second conductive material disposed on the via structure; and
a solderable material that includes a third conductive material disposed on the barrier layer;
wherein the first conductive material, the second conductive material, and the third conductive material have a different chemical composition from one another.

15. The system of claim 11 , wherein the first die or the second die are further physically coupled with a surface of the substrate.

Assignees

• Intel Corp

Inventors

• Liu Yueli
• Zhang Qinglei
• Schuckman Amanda E
• Zhang Rui

Classifications

• H10W70/618

  the bridge chips being embedded in the package substrates, interposers or redistribution layers · CPC title

• H10W74/00

  Encapsulations, e.g. protective coatings · CPC title

• H10W70/63

  Vias, e.g. via plugs · CPC title

• H10W74/15

  on active surfaces of flip-chip devices, e.g. underfills · CPC title

• H10W72/07236

  Soldering or alloying · CPC title