MOSFET active area and edge termination area charge balance

Patent metadata

Field	Value
Publication number	US-10084037-B2
Application number	US-201615339678-A
Country	US
Kind code	B2
Filing date	Oct 31, 2016
Priority date	Oct 5, 2007
Publication date	Sep 25, 2018
Grant date	Sep 25, 2018

Abstract

A method for fabricating a MOSFET having an active area and an edge termination area is disclosed. The method includes forming a first plurality of implants at the bottom of trenches located in the active area and in the edge termination area. A second plurality of implants is formed at the bottom of the trenches located in the active area. The second plurality of implants formed at the bottom of the trenches located in the active area causes the implants formed at the bottom of the trenches located in the active area to reach a predetermined concentration. In so doing, the breakdown voltage of both the active and edge termination areas can be made similar and thereby optimized while maintaining advantageous RDson.

First claim

We claim:

1. A semiconductor device, comprising:
an active area, comprising:
a plurality of active area trenches;
a source region adjacent one or more sidewalls of said plurality of active area trenches;
a gate region located adjacent to and vertically underneath said source region; and
a drain region located adjacent to and vertically underneath said gate region;

and
an edge termination area, comprising:
a gate pickup trench; and
a plurality of edge termination area trenches,

wherein a first plurality of implants are made at the bottom of trenches formed in both said active area and said edge termination area, and wherein a second plurality of implants are made at said bottom of said trenches formed in said active area and causes said implants made at the bottom of said trenches formed in said active area to reach a predetermined concentration.

2. The device of claim 1 further comprising:
a layer of oxide formed in said plurality of active area trenches; and
a layer of oxide formed in said plurality of edge termination area trenches, wherein said layer of oxide formed in said plurality of edge termination area trenches is thicker than the layer of oxide formed in said plurality of active area trenches.

3. The device of claim 2 further comprising:
a plurality of edge termination contacts in said edge termination area.

4. The device of claim 1 wherein said first and said second plurality of implants results in a simultaneous charge balance within said active area and within said edge termination area.

5. The device of claim 1 wherein said first and said second plurality of implants are phosphorous implants for N-channel devices and boron implants for P-channel devices.

6. The device of claim 1 wherein said layer of oxide formed in said active area trenches and said edge termination area trenches are formed using a low thermal oxide (LTO) process.

7. The device of claim 1 wherein said active area trenches and said edge termination area trenches are filled with doped polycrystalline.

8. The device of claim 1 wherein said source is formed over a body well comprising a voltage adjustment implant.

9. The device of claim 1 further comprising planar contacts and trench contacts that are filled with metal.

10. A semiconductor device, comprising:
an active area, comprising:
a plurality of active area trenches;
a source region adjacent one or more sidewalls of said plurality of active area trenches;
a gate region located adjacent to and vertically underneath said source region; and
a drain region located adjacent to and vertically underneath said gate region;

and
an edge termination area, comprising:
a gate pickup trench; and
a plurality of edge termination area trenches,

wherein a first plurality of implants are made at the bottom of trenches formed in both said active area and said edge termination area, and wherein a second plurality of implants are made at said bottom of said trenches formed in said active area.

11. The device of claim 10 further comprising:
a layer of oxide formed in said plurality of active area trenches; and
a layer of oxide formed in said plurality of edge termination area trenches, wherein said layer of oxide formed in said plurality of edge termination area trenches is thicker than the layer of oxide formed in said plurality of active area trenches.

12. The device of claim 11 further comprising:
a plurality of edge termination contacts in said edge termination area.

13. The device of claim 10 wherein said first and said second plurality of implants results in a simultaneous charge balance within said active area and within said edge termination area.

14. The device of claim 1 wherein said first and said second plurality of implants are phosphorous implants for N-channel devices and boron implants for P-channel devices.

15. A semiconductor device, comprising:
an active area, comprising:
a plurality of active area trenches;

and
an edge termination area, comprising:
a plurality of edge termination area trenches,

wherein a first plurality of implants are made at the bottom of trenches formed in both said active area and said edge termination area, and wherein a second plurality of implants are made at said bottom of said trenches formed in said active area.

16. The device of claim 15 further comprising:
a layer of oxide formed in said plurality of active area trenches; and
a layer of oxide formed in said plurality of edge termination area trenches, wherein said layer of oxide formed in said plurality of edge termination area trenches is thicker than the layer of oxide formed in said plurality of active area trenches.

17. The device of claim 15 wherein said active area trenches and said edge termination area trenches are filled with doped polycrystalline.

18. The device of claim 15 further comprising a source formed over a body well comprising a voltage adjustment implant.

19. The device of claim 15 further comprising planar contacts and trench contacts that are filled with metal.

20. The device of claim 1 wherein said first and said second plurality of implants are phosphorous implants for N-channel devices and boron implants for P-channel devices.

Assignees

• Vishay Siliconix

Inventors

• Chen Qufei
• Terrill Kyle
• Shi Sharon

Classifications

• H01L29/167

  Electricity · mapped topic

• H01L29/1095

  Electricity · mapped topic

• H01L29/408

  Electricity · mapped topic

• H01L29/407

  Electricity · mapped topic

• H01L29/66734

  Electricity · mapped topic