Termination for SiC trench devices

Patent metadata

Field	Value
Publication number	US-9419092-B2
Application number	US-36529106-A
Country	US
Kind code	B2
Filing date	Mar 1, 2006
Priority date	Mar 4, 2005
Publication date	Aug 16, 2016
Grant date	Aug 16, 2016

Abstract

A silicon carbide device has a termination region that includes a mesa region that links the termination region to an active area of the device and that includes one or more trenches.

First claim

What is claimed is:

1. A semiconductor device comprising:
a silicon carbide body having first and second opposing major surfaces;
an active area formed along said first major surface of said silicon carbide body;
a termination region formed along said first major surface of said silicon carbide body and defining said active area, said termination region including a termination trench formed within said silicon carbide body and having sidewalls and a bottom surface;
a guard ring formed within said silicon carbide body along said sidewalls and said bottom surface of said termination trench; and
a field insulation body covering said sidewalls and said bottom surface of said termination trench, wherein a portion of said field insulation body is in contact with said bottom of said termination trench.

2. The semiconductor device of claim 1 , further comprising a field plate disposed over said field insulation body, wherein said field plate is separate from said field insulation body.

3. The semiconductor device of claim 2 , wherein said field plate extends beyond an outer sidewall of said termination trench.

4. The semiconductor device of claim 2 , wherein said field plate is floating.

5. The semiconductor device of claim 4 , wherein said field insulation body has an opening formed therein and wherein said field plate extends through said opening and contacts said guard ring.

6. The semiconductor device of claim 2 , wherein said field plate is shorted to an electrode of said device.

7. The semiconductor device of claim 1 , wherein said termination region further includes a mesa region disposed between said termination trench and said active area, said mesa region linking said termination region to said active area.

8. The semiconductor device of claim 7 , wherein said field insulation body extends over a top surface of said mesa region.

9. The semiconductor device of claim 1 , wherein said termination region further includes an EQR ring formed along an outer peripheral edge of said device.

10. The semiconductor device of claim 1 , wherein said active area includes at least one trench formed within said silicon carbide body.

11. The semiconductor device of claim 10 , wherein said termination trench and said at least one trench of said active area extend to about a same depth within said silicon carbide body.

12. The semiconductor device of claim 1 , further comprising a conductive body disposed within said termination trench under said field insulation body.

13. The semiconductor device of claim 12 , wherein said conductive body is doped polysilicon.

14. The semiconductor device of claim 1 , wherein said semiconductor device is a transistor JFET.

15. The semiconductor device of claim 14 , further comprising a gate runner disposed between said termination trench and said active area.

16. The semiconductor device of claim 1 , wherein said termination region includes a plurality of termination trenches formed within said silicon carbide body, each termination trench having sidewalls and a bottom surface and being spaced from an adjacent termination trench by a mesa region.

17. The semiconductor device of claim 16 , wherein each of said plurality of termination trenches includes a guard ring formed within said silicon carbide body along said sidewalls and said bottom surface of said termination trench.

18. The semiconductor device of claim 17 , wherein said field insulation body covers each of said plurality of termination trenches.

19. The semiconductor device of claim 18 , further comprising a field plate disposed over said field insulation body.

20. The semiconductor device of claim 18 , further comprising a conductive body disposed within each of said termination trenches and under said field insulation body.

21. The semiconductor device of claim 20 , wherein said conductive bodies are doped polysilicon.

22. The semiconductor device of claim 18 , wherein said termination region further includes a linking mesa region that links said termination region to said active area.

23. The semiconductor device of claim 18 , wherein said termination region further includes an EQR ring formed along an outer peripheral edge of said device.

24. The semiconductor device of claim 16 , wherein said active area includes at least one trench formed within said silicon carbide body.

25. The semiconductor device of claim 24 , wherein each of said termination trenches and said at least one trench of said active area extend to about a same depth within said silicon carbide body.

26. The semiconductor device of claim 16 , wherein said semiconductor device is a transistor JFET.

Assignees

• Carta Rossano
• Bellemo Laura
• Vishay Siliconix

Inventors

• Carta Rossano
• Bellemo Laura

Classifications

• H10D30/051

  of FETs having PN junction gates (H10D30/015 takes precedence) · CPC title

• H10D30/831 Primary

  Vertical FETs having PN junction gate electrodes (Vertical SIT H10D30/202) · CPC title

• H10D64/311

  Gate electrodes for field-effect devices · CPC title

• H10D64/111

  Field plates · CPC title

• H10D62/106

  having supplementary regions doped oppositely to or in rectifying contact with regions of the semiconductor bodies, e.g. guard rings with PN or Schottky junctions · CPC title