Adaptive charge balanced edge termination

Patent metadata

Field	Value
Publication number	US-9842911-B2
Application number	US-201213484114-A
Country	US
Kind code	B2
Filing date	May 30, 2012
Priority date	May 30, 2012
Publication date	Dec 12, 2017
Grant date	Dec 12, 2017

Abstract

In one embodiment, a semiconductor device can include a substrate including a first type dopant. The semiconductor device can also include an epitaxial layer located above the substrate and including a lower concentration of the first type dopant than the substrate. In addition, the semiconductor device can include a junction extension region located within the epitaxial layer and including a second type dopant. Furthermore, the semiconductor device can include a set of field rings in physical contact with the junction extension region and including a higher concentration of the second type dopant than the junction extension region. Moreover, the semiconductor device can include an edge termination structure in physical contact with the set of field rings.

First claim

What is claimed is:

1. A semiconductor device comprising:
a substrate comprising a first type dopant;
an epitaxial layer located above said substrate and comprising a lower concentration of said first type dopant than said substrate;
an edge termination comprising:
a junction extension region located within said epitaxial layer and comprising a second type dopant;
a field ring formed into said junction extension region, said field ring comprising a higher concentration of said second type dopant than said junction extension region; and
a field plate formed above and in physical contact with said field ring, said field plate comprises a metal and a polysilicon that are both located above and extend beyond said junction extension region.

2. The semiconductor device of claim 1 , wherein said edge termination further comprises a plurality of metal field plates.

3. The semiconductor device of claim 1 , wherein said edge termination further comprises a plurality of polysilicon field plates.

4. The semiconductor device of claim 1 , wherein said junction extension region comprises laterally varying doping of said second type dopant.

5. The semiconductor device of claim 1 , wherein said field plate is in ohmic contact with said junction extension region.

6. The semiconductor device of claim 1 , wherein said edge termination further comprising a tub region located within said epitaxial layer and comprising said second type dopant.

7. The semiconductor device of claim 1 , wherein said edge termination further comprising a tub region located within said epitaxial layer and comprising said second type dopant, said tub region in contact with and laterally adjacent to said junction extension region and extends deeper than said junction extension region.

8. A metal oxide semiconductor field effect transistor (MOSFET) device comprising:
a substrate comprising a first type dopant;
an epitaxial layer located above said substrate and comprising a lower concentration of said first type dopant than said substrate;
an edge termination comprising:
a junction extension region located within said epitaxial layer and comprising a second type dopant;
a plurality of field rings formed into said junction extension region, each of said plurality of field rings comprising a higher concentration of said second type dopant than said junction extension region; and
a plurality of field plates, a field plate of said plurality of field plates is formed above and in physical contact with a field ring of said plurality of field rings, said field plate comprises a metal and a polysilicon that are both located above and extend beyond said junction extension region.

9. The MOSFET device of claim 8 , wherein each of said plurality of field plates comprises metal.

10. The MOSFET device of claim 8 , wherein each of said plurality of field plates comprises polysilicon.

11. The MOSFET device of claim 8 , wherein said junction extension region comprises laterally varying doping of said second type dopant.

12. The MOSFET device of claim 8 , wherein said edge termination further comprising a tub region located within said epitaxial layer and comprising said second type dopant.

13. The MOSFET device of claim 8 , wherein said edge termination further comprising a tub region located within said epitaxial layer and comprising said second type dopant, said tub region in contact with and laterally adjacent to said junction extension region.

14. The MOSFET device of claim 8 , wherein said edge termination further comprising a gate runner.

15. A semiconductor device comprising:
a substrate comprising a first type dopant;
an epitaxial layer located above said substrate and comprising a lower concentration of said first type dopant than said substrate;
an edge termination comprising:
a junction extension region located within said epitaxial layer and comprising a second type dopant, said junction extension region comprises laterally varying doping of said second type dopant;
a tub region located within said epitaxial layer and comprising said second type dopant;
a field ring formed into said junction extension region, said field ring comprising a higher concentration of said second type dopant than said junction extension region; and
a field plate formed above and in physical contact with said field ring, said field plate comprises a metal and a polysilicon that are both located above and extend beyond said junction extension region.

16. The semiconductor device of claim 15 , wherein said edge termination further comprises a plurality of metal field plates.

17. The semiconductor device of claim 15 , wherein said edge termination further comprises a plurality of polysilicon field plates.

18. The semiconductor device of claim 15 , wherein said field plate is in ohmic contact with said junction extension region.

19. The semiconductor device of claim 15 , wherein said edge termination further comprises a plurality of field rings formed into said junction extension region.

20. The semiconductor device of claim 15 , said tub region extends deeper than said junction extension region.

Assignees

• Tipirneni Naveen
• Pattanayak Deva N
• Vishay Siliconix

Inventors

• Tipirneni Naveen
• Pattanayak Deva N

Classifications

• H10P30/22 Primary

  using masks · CPC title

• H01L29/66712 Primary

  Electricity · mapped topic

• H01L29/404

  Electricity · mapped topic

• H01L29/0619

  Electricity · mapped topic

• H01L29/0615

  Electricity · mapped topic