Apparatus and method for low-latency invocation of accelerators

Patent metadata

Field	Value
Publication number	US-10083037-B2
Application number	US-201615281944-A
Country	US
Kind code	B2
Filing date	Sep 30, 2016
Priority date	Dec 28, 2012
Publication date	Sep 25, 2018
Grant date	Sep 25, 2018

Abstract

An apparatus and method are described for providing low-latency invocation of accelerators. For example, a processor according to one embodiment comprises: a plurality of simultaneous multithreading (SMT) cores, at least one shared cache circuit to be shared among the SMT cores, and at least one L2 cache circuit to store both instructions and data. The processor further comprises a communication interconnect circuit including a PCIe circuit to communicatively couple one or more of the SMT cores to an accelerator device, the PCIe circuit to provide the accelerator device access to resources of the processor including the at least one shared cache circuit. The processor further comprises a memory access circuit to identify an accelerator context save/restore region in a memory determined by an accelerator context save/restore value, the accelerator context save/restore region to store an accelerator context state.

First claim

What is claimed is:

1. A processor comprising:
a plurality of simultaneous multithreading (SMT) cores, each of the SMT cores to perform out-of-order instruction execution for a plurality of threads;
at least one shared cache circuit to be shared among two or more of the SMT cores;
at least one of the SMT cores comprising:
an instruction fetch circuit to fetch instructions of one or more of the threads,
an instruction decode circuit to decode the instructions,
a register renaming circuit to rename registers of a register file,
an instruction cache circuit to store instructions to be executed, and
a data cache circuit to store data;

at least one level 2 (L2) cache circuit to store both instructions and data and communicatively coupled to the instruction cache circuit and the data cache circuit;
a communication interconnect circuit including a peripheral component interconnect express (PCIe) circuit, the PCIe circuit to communicatively couple one or more of the SMT cores to an accelerator device, the PCIe circuit to provide the accelerator device access to resources of the processor including the at least one shared cache circuit; and
a memory access circuit to identify an accelerator context save/restore region of the accelerator device in a memory space that stores data from execution of an application, the application invoking the accelerator device during the application's execution, the accelerator context save/restore region pointed by a context save/restore pointer, and the accelerator context save/restore region to store an accelerator context state.

2. The processor as in claim 1 wherein the accelerator device is to restore its context state from the accelerator context save/restore region.

3. The processor as in claim 1 wherein the context save/restore pointer identifies a memory address.

4. The processor as in claim 1 further comprising:
a register to store the accelerator context save/restore pointer.

5. A method comprising:
performing out-of-order instruction execution for a plurality of threads on a plurality of simultaneous multithreading (SMT) cores;
sharing at least one shared cache among two or more of the SMT cores;
fetching instructions of one or more of the threads;
decoding the instructions;
renaming registers of a register file;
storing instructions to be executed in an instruction cache circuit;
storing data in a data cache circuit;
storing both instructions and data in at least one level 2 (L2) cache circuit communicatively coupled to the instruction cache circuit and the data cache circuit;
communicatively coupling one or more of the SMT cores to an accelerator device, wherein the one or more SMT cores are communicatively coupled to the accelerator device through a peripheral component interconnect express (PCIe) circuit;
providing the accelerator device access to resources of a processor including the at least one shared cache circuit through the PCIe circuit; and
identifying an accelerator context save/restore region of the accelerator device in a memory space that stores data from execution of an application, the application invoking the accelerator device during the application's execution, the accelerator context save/restore region pointed by a context save/restore pointer, and the accelerator context save/restore region to store an accelerator context state.

6. The method as in claim 5 wherein the accelerator device is to restore its context state from the accelerator context save/restore region.

7. The method as in claim 5 wherein the context save/restore pointer identifies a memory address.

8. The method as in claim 5 further comprising:
storing the accelerator context save/restore pointer in a register.

9. An apparatus comprising:
means for performing out-of-order instruction execution for a plurality of threads on a plurality of simultaneous multithreading (SMT) cores;
means for sharing at least one shared cache among two or more of the SMT cores;
means for fetching instructions of one or more of the threads;
means for decoding the instructions;
means for renaming registers of a register file;
means for storing instructions to be executed in an instruction cache circuit;
means for storing data in a data cache circuit;
means for storing both instructions and data in at least one level 2 (L2) cache circuit communicatively coupled to the instruction cache circuit and the data cache circuit;
means for communicatively coupling one or more of the SMT cores to an accelerator device, the means for communicatively coupling one or more of the SMT cores to the accelerator device includes a peripheral component interconnect express (PCIe) circuit;
means for providing the accelerator device access to resources of the apparatus including the at least one shared cache through the PCIe circuit; and
means for identifying an accelerator context save/restore region in a memory space that stores data from execution of an application, the application invoking the accelerator device during the application's execution, the accelerator context save/restore region pointed by a context save/restore pointer, and the accelerator context save/restore region to store an accelerator context state.

10. The apparatus as in claim 9 wherein the accelerator device is to restore its context state from the accelerator context save/restore region.

11. The apparatus as in claim 9 wherein the context save/restore pointer identifies a memory address.

12. The apparatus as in claim 9 further comprising:
a register to store the accelerator context save/restore pointer.

Assignees

• Intel Corp

Inventors

• Ben-Kiki Oren
• Pardo Ilan
• Valentine Robert
• Weissmann Eliezer
• Markovich Dror
• Yosef Yuval

Classifications

• G06F9/30101

  Special purpose registers · CPC title

• G06F9/3802 Primary

  Instruction prefetching · CPC title

• G06F11/0721

  within a central processing unit [CPU] · CPC title

• G06F9/30145 Primary

  Instruction analysis, e.g. decoding, instruction word fields · CPC title

• G06F11/0772

  Means for error signaling, e.g. using interrupts, exception flags, dedicated error registers · CPC title