Apparatus and method for a hybrid latency-throughput processor

Patent metadata

Field	Value
Publication number	US-9417873-B2
Application number	US-201213730055-A
Country	US
Kind code	B2
Filing date	Dec 28, 2012
Priority date	Dec 28, 2012
Publication date	Aug 16, 2016
Grant date	Aug 16, 2016

Abstract

An apparatus and method are described for executing both latency-optimized execution logic and throughput-optimized execution logic on a processing device. For example, a processor according to one embodiment comprises: latency-optimized execution logic to execute a first type of program code; throughput-optimized execution logic to execute a second type of program code, wherein the first type of program code and the second type of program code are designed for the same instruction set architecture; logic to identify the first type of program code and the second type of program code within a process and to distribute the first type of program code for execution on the latency-optimized execution logic and the second type of program code for execution on the throughput-optimized execution logic.

First claim

What is claimed is:

1. A processor comprising:
latency-optimized execution logic to execute a first type of program code;
throughput-optimized execution logic to execute a second type of program code, wherein the first type of program code and the second type of program code are designed for the same instruction set architecture;
logic to identify the first type of program code and the second type of program code within a process and to distribute the first type of program code for execution on the latency-optimized execution logic and the second type of program code for execution on the throughput-optimized execution logic.

2. The processor as in claim 1 wherein the throughput-optimized execution logic comprises a plurality of processing elements (PEs), each PE adapted to execute the second type of program code.

3. The processor as in claim 2 wherein each PE is capable of simultaneous multithreading for multiple threads of the second type of program code.

4. The processor as in claim 1 wherein the throughput-optimized execution logic comprises a front end unit for distributing threads of the second type of program code to a plurality of processing elements (PEs).

5. The processor as in claim 4 wherein the PEs are homogeneous processing elements, each capable of executing any portion of the second type of program code.

6. The processor as in claim 4 wherein the PEs are heterogeneous processing elements, wherein some of the PEs can execute some, but not all of the second type of program code.

7. The processor as in claim 4 wherein each thread of the second type of program code has a separate instruction pointer associated therewith.

8. The processor as in claim 1 wherein the throughput-optimized execution logic has a shared front end and plurality of execution units.

9. The processor as in claim 1 wherein an instruction of the first type of program code triggers the throughput-optimized execution logic which, in turn, invokes the execution of the second type of program code.

10. The processor as in claim 1 wherein the process comprises an application program.

Assignees

• Intel Corp

Inventors

• Ben-Kiki Oren
• Yosef Yuval
• Pardo Ilan
• Markovich Dror

Classifications

• G06F15/7892

  Reconfigurable logic embedded in CPU, e.g. reconfigurable unit · CPC title

• G06F9/3836

  Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution · CPC title

• G06F15/80

  comprising an array of processing units with common control, e.g. single instruction multiple data processors (G06F15/82 takes precedence {; for correlation function computation G06F17/15}) · CPC title

• G06F15/7867

  with reconfigurable architecture · CPC title

• G06F9/3861

  Recovery, e.g. branch miss-prediction, exception handling (error detection or correction G06F11/00) · CPC title