Technologies for dividing work across accelerator devices
US-2024143410-A1 · May 2, 2024 · US
Generating hardware accelerators and processor offloads
US9003166B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-9003166-B2 |
| Application number | US-201213358407-A |
| Country | US |
| Kind code | B2 |
| Filing date | Jan 25, 2012 |
| Priority date | Dec 1, 2006 |
| Publication date | Apr 7, 2015 |
| Grant date | Apr 7, 2015 |
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- Title
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Abstract
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System and method for generating hardware accelerators and processor offloads. System for hardware acceleration. System and method for implementing an asynchronous offload. Method of automatically creating a hardware accelerator. Computerized method for automatically creating a test harness for a hardware accelerator from a software program. System and method for interconnecting hardware accelerators and processors. System and method for interconnecting a processor and a hardware accelerator. Computer implemented method of generating a hardware circuit logic block design for a hardware accelerator automatically from software. Computer program and computer program product stored on tangible media implementing the methods and procedures of the invention.
First claim
Opening claim text (preview).
The invention claimed is: 1. A method of automatically generating an accelerator comprising: generating a parameter queue, directly coupled to a host processor, for receiving one or more function parameters from the host processor and allowing the queuing of accelerator tasks; generating a result queue, directly coupled to the host processor, for returning one or more result values to the host processor; generating a logic for: carrying out a software function in hardware,…
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- G06F9/5044Primary
Physics · mapped topic
- G06F9/54Primary
Physics · mapped topic
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- What does patent US9003166B2 cover?
- System and method for generating hardware accelerators and processor offloads. System for hardware acceleration. System and method for implementing an asynchronous offload. Method of automatically creating a hardware accelerator. Computerized method for automatically creating a test harness for a hardware accelerator from a software program. System and method for interconnecting hardware accele…
- Who is the assignee on this patent?
- Sinha Navendu, Jordan William Charles, Moyer Bryon Irwin, and 6 more
- What technology area does this patent fall under?
- Primary CPC classification G06F9/5044. Mapped technology areas include Physics.
- When was this patent published?
- Publication date Tue Apr 07 2015 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
- What related patents are in patentsdb?
- We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).