GPU work creation and stateless graphics in OPENGL

Patent metadata

Field	Value
Publication number	US-9275491-B2
Application number	US-201113078878-A
Country	US
Kind code	B2
Filing date	Apr 1, 2011
Priority date	Apr 5, 2010
Publication date	Mar 1, 2016
Grant date	Mar 1, 2016

Abstract

One embodiment of the present invention sets forth a method for generating work to be processed by a graphics pipeline residing within a graphics processor. The method includes the steps of receiving an indication that a first graphics workload is to be submitted to a command queue associated with the graphics processor, allocating a first portion of shader accessible memory for one or more units of state information that are necessary for processing the first graphics workload, populating the first portion of shader accessible memory with the one or more units of state information, and transmitting to the command queue of the graphics processor the one or more units of state information stored within the first portion of shader accessible memory, wherein the first graphics workload is processed within the graphics pipeline based on the one or more units of state information.

First claim

We claim:

1. A computer-implemented method for generating work to be processed by a graphics pipeline residing within a graphics processor, the method comprising:
receiving an indication that a first graphics workload is to be submitted to a command queue associated with the graphics processor;
allocating, via a first shader thread, a first portion of shader accessible memory for one or more units of state information that are related to processing the first graphics workload;
populating, via the first shader thread, the first portion of memory with the one or more units of state information;
sorting the first graphics workload and a second graphics workload in an order of execution based on the one or more units of state information and on state information related to processing the second graphics workload; and
transmitting to the command queue of the graphics processor the one or more units of state information stored within the first portion of memory and the state information related to processing the second graphics workload, wherein the first graphics workload and the second graphics workload are processed within the graphics pipeline in the order of execution.

2. The method of claim 1 , further comprising receiving a handle to a first pre-compiled state object that includes at least one unit of state information associated with the first graphics workload.

3. The method of claim 2 , wherein the size of the first portion of the memory is based on the size of the first pre-compiled state object.

4. The method of claim 2 , wherein populating the first portion of memory comprises copying the first pre-compiled state object to the first portion of memory via the handle to the first pre-compiled state object.

5. The method of claim 2 , wherein populating the first portion of memory includes computing and storing the values of dynamic state associated with the first pre-compiled state object.

6. The method of claim 2 , wherein the at least one unit of state information associated with the first graphics workload is compressed, and the at least one unit of state information is decompressed before the first graphics workload is processed by the graphics processor.

7. The method of claim 1 , further comprising transmitting to the command queue a second command and state information associated with the second command received from an application program executing on a second processor.

8. The method of claim 7 , wherein the second command is transmitted to the command queue after the first graphics workload has been transmitted to the command queue, and the second command is not processed until the graphics processor processes the first graphics workload.

9. The method of claim 7 , wherein the state information associated with the second command is inherited for processing the first graphics workload.

10. The method of claim 1 , wherein a plurality of threads that includes the first shader thread executes within a shader engine, and each of the threads performs the steps of receiving, allocating and populating in parallel with one another.

11. The method of claim 10 , wherein the threads further perform the step of transmitting in parallel with one another.

12. The method of claim 10 , wherein the threads further perform the step of transmitting serially to one another.

13. The method of claim 1 , wherein the first graphics workload is self-contained and does not depend on state information corresponding to a second graphics workload.

14. The method of claim 1 , wherein at least one unit of state information related to processing the first graphics workload can be accessed from the memory via bindless memory access.

15. The method of claim 1 , wherein a first unit of state information stored within the first portion of memory was previously transmitted to the graphics processor, and further comprising filtering the one or more units of state information such that the first unit of state information is not transmitted to the graphics processor.

16. The method of claim 1 , wherein sorting the first graphics workload and the second graphics workload in the order of execution comprises selecting the order in which the first graphics workload and the second graphics workload are processed by the graphics pipeline.

17. The method of claim 1 , wherein the one or more units of state information that are related to processing the first graphics workload include at least one of a reference to a pre-compiled state object associated with the first graphics workload, values of dynamic state parameters associated with the first graphics workload, values of environment parameters associated with the first graphics workload, and values of different parameters of the indication.

18. A non-transitory computer-readable storage medium storing instructions that, when executed by a processor, cause the processor to execute a plurality of threads that includes a first shader thread and to generate work to be processed by a graphics pipeline residing within a graphics processor, by performing the steps of:
receiving an indication that a first graphics workload is to be submitted to a command queue associated with the graphics processor;
allocating, via the first shader thread, a first portion of shader accessible memory for one or more units of state information that are related to processing the first graphics workload;
populating, via the first shader thread, the first portion of memory with the one or more units of state information;
sorting the first graphics workload and a second graphics workload in an order of execution based on the one or more units of state information and on state information related to processing the second graphics workload; and
transmitting to the command queue of the graphics processor the one or more units of state information stored within the first portion of memory and the state information related to processing the second graphics workload, wherein the first graphics workload and the second graphics workload are processed within the graphics pipeline in the order of execution.

19. The computer-readable medium of claim 18 , further comprising transmitting to the command queue a second command and state information associated with the second command received from an application program executing on a second processor.

20. The computer-readable medium of claim 19 , wherein the second command is transmitted to the command queue after the first graphics workload has been transmitted to the command queue, and the second command is not processed until the graphics processor processes the first graphics workload.

21. The computer-readable medium of claim 19 , wherein the state information associated with the second command is inherited for processing the first graphics workload.

22. The computer-readable medium of claim 18 , wherein a plurality of threads that includes the first shader thread executes within a shader engine, and each of the threads performs the steps of receiving, allocating and populating in parallel with one another.

23. The computer-readable medium of claim 18 , wherein the first graphics workload is self-contained and does not depend on state information corresponding to a second graphics workload.

24. The computer-readable medium of claim 18 , wherein at least one unit of state information related to processing the first graphics workload can be accessed from the memory via bindless memory access.

Assignees

• Bolz Jeffrey A
• Hall Jesse David
• Duluk Jr Jerome F
• Brown Patrick R
• Palmer Gregory Scott
• Nvidia Corp

Inventors

• Bolz Jeffrey A
• Hall Jesse David
• Duluk Jr Jerome F
• Brown Patrick R
• Palmer Gregory Scott

Classifications

• G06T15/80

  Shading · CPC title

• G06T1/60

  Memory management · CPC title

• G06F9/3009

  Thread control instructions · CPC title

• G06F9/3879

  for non-native instruction execution, e.g. executing a command; for Java instruction set · CPC title

• G06T15/005 Primary

  General purpose rendering architectures · CPC title