Apparatus, system and method of communication during a transmit opportunity (TXOP)
US-11743761-B2 · Aug 29, 2023 · US
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Markovich Dror patents
Markovich Dror is listed as an inventor on 23 patents in our database. Major assignees and classification codes are summarized below.
| Metric | Value |
|---|---|
| Inventor | Markovich Dror |
| Total patents | 23 |
| First publication | Aug 6, 2015 |
| Latest publication | Aug 29, 2023 |
Notable patents
Publications ranked by popularity score, then publication date.
Communication scanning method and system
US-11329706-B2 · May 10, 2022 · US
Apparatus, system and method of communication during a transmit opportunity (txop)
US-2022060936-A1 · Feb 24, 2022 · US
Apparatus, system and method of communication during a transmit opportunity (TXOP)
US-11178570-B2 · Nov 16, 2021 · US
Communication scanning method and system
US-2021234596-A1 · Jul 29, 2021 · US
Apparatus, system and method of communication during a transmit opportunity (txop)
US-2020275307-A1 · Aug 27, 2020 · US
Apparatus and method for a hybrid latency-throughput processor
US-10664284-B2 · May 26, 2020 · US
Apparatus and method for a hybrid latency-throughput processor
US-2019196838-A1 · Jun 27, 2019 · US
Processing core having shared front end unit
US-2019171462-A1 · Jun 6, 2019 · US
Apparatus and method for a hybrid latency-throughput processor
US-10255077-B2 · Apr 9, 2019 · US
Recent patents
Latest publications not already listed above.
Processing core having shared front end unit
US-10140129-B2 · Nov 27, 2018 · US
Vector mask driven clock gating for power efficiency of a processor
US-10133577-B2 · Nov 20, 2018 · US
Apparatus and method for low-latency invocation of accelerators
US-10095521-B2 · Oct 9, 2018 · US
Apparatus and method for low-latency invocation of accelerators
US-10089113-B2 · Oct 2, 2018 · US
Apparatus and method for low-latency invocation of accelerators
US-10083037-B2 · Sep 25, 2018 · US
Apparatus and method for low-latency invocation of accelerators
US-2017017491-A1 · Jan 19, 2017 · US
Apparatus and method for low-latency invocation of accelerators
US-2017017492-A1 · Jan 19, 2017 · US
Apparatus and Method for a Hybrid Latency-Throughput Processor
US-2016342419-A1 · Nov 24, 2016 · US
Apparatus and method for low-latency invocation of accelerators
US-2016246597-A1 · Aug 25, 2016 · US
Apparatus and method for a hybrid latency-throughput processor
US-9417873-B2 · Aug 16, 2016 · US
Apparatus and method for low-latency invocation of accelerators
US-9361116-B2 · Jun 7, 2016 · US
Apparatus and method for memory-mapped register caching
US-9189398-B2 · Nov 17, 2015 · US
Vector mask driven clock gating for power efficiency of a processor
US-2015220345-A1 · Aug 6, 2015 · US
Major assignees
Companies most often associated with this inventor's publications.
| Assignee | Patents |
|---|---|
| Intel Corp | 19 |
| Ben-Kiki Oren | 3 |
| Valentine Robert | 3 |
| Weissmann Eliezer | 3 |
| Markovich Dror | 3 |
Top CPC classifications
Most common classification codes across this inventor's patents.
| CPC | Patents |
|---|---|
| G06F9/3877 | 12 |
| G06F9/3802 | 9 |
| G06F12/0875 | 8 |
| G06F2212/452 | 7 |
| G06F11/0721 | 7 |