Semiconductor device

Patent metadata

Field	Value
Publication number	US-9883129-B2
Application number	US-201615274312-A
Country	US
Kind code	B2
Filing date	Sep 23, 2016
Priority date	Sep 25, 2015
Publication date	Jan 30, 2018
Grant date	Jan 30, 2018

Abstract

The present invention provides a semiconductor device which enables data compression with a small amount of data. The present invention is a semiconductor device which includes a pixel portion, a memory, a first circuit, and a second circuit. The pixel portion has a function of obtaining imaging data. The first circuit has a function of performing discrete cosine transform on the imaging data, and generating first data. The first data is analog data, and the memory has a function of retaining the first data. The second circuit has a function of performing discrete cosine transform on the first data, and generating second data. The memory includes a first transistor, which includes an oxide semiconductor in a channel formation region, and a second transistor, in which a channel formation region is provided in a Si wafer.

First claim

What is claimed is:

1. A semiconductor device comprising:
a pixel portion configured to obtain an imaging data;
a first circuit configured to perform discrete cosine transform on the imaging data and generate a first data which is an analog data;
a memory configured to store the first data; and
a second circuit configured to perform discrete cosine transform on the first data and generate a second data.

2. The semiconductor device according to claim 1 ,
wherein the pixel portion comprises a photodiode and a transistor, and
wherein a channel formation region of the transistor comprises an oxide semiconductor.

3. The semiconductor device according to claim 1 , wherein each of the first circuit and the second circuit is an analog processing circuit.

4. The semiconductor device according to claim 1 ,
wherein the first circuit is configured to perform discrete cosine transform in one of the x-axis direction and the y-axis direction on the imaging data, and
wherein the second circuit is configured to perform discrete cosine transform in the other of the x-axis direction and the y-axis direction on the first data.

5. The semiconductor device according to claim 1 ,
wherein the memory comprises a first transistor, a second transistor, and a capacitor,
wherein a channel formation region of the first transistor comprises an oxide semiconductor, and
wherein a channel formation region of the second transistor comprises silicon.

6. A camera module comprising:
the semiconductor device according to claim 1 ; and
a lens.

7. A semiconductor device comprising:
a pixel portion configured to obtain a first imaging data, a second imaging data, and a third imaging data which is a difference between the first imaging data and the second imaging data;
a first circuit configured to perform discrete cosine transform on the third imaging data and generate a first data which is an analog data;
a memory configured to store the first data; and
a second circuit configured to perform discrete cosine transform on the first data and generate a second data.

8. The semiconductor device according to claim 7 ,
wherein the pixel portion comprises a photodiode and a transistor, and
wherein a channel formation region of the transistor comprises an oxide semiconductor.

9. The semiconductor device according to claim 7 , wherein each of the first circuit and the second circuit is an analog processing circuit.

10. The semiconductor device according to claim 7 ,
wherein the first circuit is configured to perform discrete cosine transform in one of the x-axis direction and the y-axis direction on the third imaging data, and
wherein the second circuit is configured to perform discrete cosine transform in the other of the x-axis direction and the y-axis direction on the first data.

11. The semiconductor device according to claim 7 ,
wherein the memory comprises a first transistor, a second transistor, and a capacitor,
wherein a channel formation region of the first transistor comprises an oxide semiconductor, and
wherein a channel formation region of the second transistor comprises silicon.

12. A camera module comprising:
the semiconductor device according to claim 7 ; and
a lens.

Assignees

• Semiconductor Energy Lab

Inventors

• Kurokawa Yoshiyuki

Classifications

• H04N25/77 Primary

  Pixel circuitry, e.g. memories, A/D converters, pixel amplifiers, shared circuits or shared components · CPC title

• H04N9/8042

  involving data reduction · CPC title

• H01L27/14627

  Electricity · mapped topic

• H04N5/3745 Primary

  Electricity · mapped topic

• H01L27/14616

  Electricity · mapped topic