Integrated circuit device with reconfigurable digital filter circuits

Patent metadata

Field	Value
Publication number	US-10033403-B1
Application number	US-201514736488-A
Country	US
Kind code	B1
Filing date	Jun 11, 2015
Priority date	Nov 25, 2014
Publication date	Jul 24, 2018
Grant date	Jul 24, 2018

Abstract

An integrated circuit device can include at least one input; at least one output configured to provide a multi-bit output value; at least one input; at least one output configured to provide a multi-bit output value; a plurality of configurable digital filter circuits; and switch circuits coupled to the at least one input and to the at least one output, the switch circuits configurable to connect same digital filter circuits as a single processing path or separate processing paths.

First claim

What is claimed is:

1. An integrated circuit (IC) device, comprising:
at least one input;
at least one output configured to provide a multi-bit output value;
a plurality of configurable digital filter circuits; and
switch circuits coupled to the at least one input and to the at least one output, the switch circuits configurable to connect, in series, the same digital filter circuits as a single processing path between the at least one input and the at least one output or as separate processing paths between the at least one input and the at least one output;
wherein the switch circuits are coupled to a configuration data input, and wherein the switch circuits are configured to enable and disable the single processing path and the separate processing paths according to configuration data received at the configuration data input;
wherein the same digital filter circuits have different characteristics when configured as the single processing path than when configured as the separate processing paths, and wherein the different characteristics include a decimation order or a decimation ratio.

2. The IC device of claim 1 , further including:
a sigma-delta modulator circuit configured to receive an analog input signal and provide a modulated output signal corresponding to the analog input signal; and
the at least on input is configured to receive the modulated output signal.

3. The IC device of claim 1 , further including:
an input multiplexer (MUX) having at least a first MUX input coupled to an external connection to the IC device, a second MUX input coupled to a sigma-delta modulator circuit of the IC device, a third MUX input coupled to another circuit of the IC device, and a MUX output coupled to the at least one input.

4. The IC device of claim 1 , wherein:
the at least one output includes a plurality of outputs, each configured to provide its own multi-bit output value; and
the switch circuits are configurable to connect the configurable digital filter circuits into separate, parallel, digital processing paths, each coupled to a different output and to connect digital filter circuits in series with one another.

5. The IC device of claim 1 , wherein:
the configurable digital filter circuits are configurable into sinc filter circuits, each having an order and down sampling rate.

6. The IC device of claim 1 , wherein:
the configurable digital filter circuits include a plurality of different circuit sections configurable for interconnection with one another by the switch circuits to form different digital filter circuit types or different numbers of digital filter circuits.

7. The IC device of claim 6 , wherein:
the different circuit sections include multi-bit registers configured to receive and output multi-bit values in parallel with one another, multi-bit arithmetic logic units (ALUs), and frequency divider circuits.

8. The IC device of claim 7 , wherein:
the different circuit sections are configurable into sinc filter circuits, the order of a sinc filter being configurable according to series connected register stages, a decimation ratio of a sinc filter being configurable according to a down sample frequency.

9. The IC device of claim 7 , wherein:
the different circuit sections further include programmable multiplier sections configurable for interconnection with other of the circuit sections; and
the multiplier sections are configurable for inclusion into digital filter circuits to add zeros with respect to a frequency response of the digital filter circuits according to programmable multiplier values.

10. The IC device of claim 7 , wherein:
the different circuit sections are further configurable into finite impulse response filters configured to modify a frequency response of other filters formed with the different circuit sections.

11. The IC device of claim 7 , wherein:
the different circuit sections are further configurable into non-filter circuits.

12. The IC device of claim 11 , further including:
a reconstruction filter circuit coupled to the different circuit sections and configured to generate an analog output signal in response to a multi-bit digital value from the different circuit sections;
wherein the non-filter circuit and the reconstruction filter circuit form at least part of an oversampling digital-to-analog converter.

13. A method for implementing digital filtering functions in an integrated circuit (IC) device, the method comprising:
receiving configuration data at a configuration data input in the IC device; and
in response to the configuration data, configuring in series a plurality of digital filter circuit sections into a single processing path or separate processing paths, wherein the configuring includes enabling and disabling the single processing path and the separate processing paths according to the configuration data;
wherein the plurality of digital filter circuit sections have different characteristics when configured into the single processing path than when configured into the separate processing paths, and wherein the different characteristics include a decimation order or a decimation ratio;
wherein the processing paths are connected between at least one input and at least one output configured to provide a multi-bit output value and are formed in the IC device.

14. The method of claim 13 , wherein:
configuring the plurality of digital filter circuit sections includes configuring switch circuits that interconnect digital filter circuit components to one another;
wherein the digital filter circuit components are selected from the group of registers and at least one arithmetic logic circuit.

15. The method of claim 13 , wherein:
the configurable digital filter circuits are configurable into any of a plurality of sinc filters, each having a selectable order and decimation ratio.

16. The method of claim 13 , further including:
the plurality of digital filter sections are configured into a plurality of separate processing paths; and
multiplexing data values received at the same input between different ones of the processing paths.

17. The method of claim 13 , further including:
sigma-delta modulating an analog input value to generate a modulated signal; and
digitally filtering the modulated signal with at least one of the processing path to generate an analog-to-digital conversion value corresponding to the analog input value.

18. A method, comprising:
receiving at least one modulated input bit stream;
filtering the at least one input bit stream with digital filter circuits configured from a plurality of different circuit sections interconnected in series with one another by switch circuits according to configuration data received at a configuration data input into a single processing path or separate processing paths, wherein the single processing path and the separate processing paths are enabled and disabled according to the configuration data;
providing multi-bit filter output data from the digital filter circuits on at least one output;
wherein characteristics of the digital filter circuits are configurable and include a decimation order or a decimation ratio, and the circuit sections include clocked registers and at least one arithmetic logic unit; and
wherein the characteristics of the digital filter circuits when configured into the single processing path are different from the characteristics of the digital filter circuits when configured into the separate processing paths.

19. The method of claim 18 , wherein:
receiving at least one

Assignees

• Cypress Semiconductor Corp

Inventors

• Thiagarajan Eashwar
• Vanitegem Jean-Paul
• Kutz Harold M
• Pai Maroor Anasuya
• Castor-Perry Kendall V

Classifications

• H03H17/0664

  where the output-delivery frequency is lower than the input sampling frequency, i.e. decimation · CPC title

• H03M3/466

  Multiplexed conversion systems · CPC title

• H03M3/462 Primary

  Details relating to the decimation process (decimation filters in general H03H17/0416, H03H17/0621) · CPC title

• H03H17/0416

  with input-sampling frequency and output-delivery frequency which differ, e.g. extrapolation; Anti-aliasing · CPC title

• H03H17/0657

  where the output-delivery frequency is higher than the input sampling frequency, i.e. interpolation · CPC title