Circuit layout for thin film transistors in series or parallel

Patent metadata

Field	Value
Publication number	US-10020457-B2
Application number	US-201715652554-A
Country	US
Kind code	B2
Filing date	Jul 18, 2017
Priority date	Nov 8, 2012
Publication date	Jul 10, 2018
Grant date	Jul 10, 2018

Abstract

A thin film device has a source region, a drain region, a first gate disposed between the source region and the drain region, a second gate disposed between the source region and the drain region, wherein the second gate region is in close proximity with the first gate region, a semiconductor film disposed between the source region, the drain region, and the first and second gate regions, and a dielectric material disposed between the source region, the drain region, the first and second gate regions, and the semiconductor film.

First claim

The invention claimed is:

1. A thin film device, comprising:
a single source region;
a single drain region;
a first gate disposed between the single source region and the single drain region, the first gate having interconnects;
a second gate disposed between the single source region and the single drain region, wherein the second gate region is in close proximity with the first gate region and the first and second gates are aligned in a row, the second gate having interconnects, wherein the first gate and the second gate define first and second transistors using the single source region and the single drain region; and
a semiconductor film deposited from a solution forming a channel region, disposed between the single source region, the single drain region, and the first and second gate regions.

2. The device of claim 1 , further comprising a plurality of tertiary gates wherein each of the plurality of tertiary gates is parallel to one another and each is disposed between the single source region and the single drain region.

3. The device of claim 2 , wherein the semiconductor is further comprised of two semiconductor regions, one having n-type polarity and the other having p-type polarity.

4. The device of claim 2 , wherein a portion of the semiconductor material having p-type polarity and a portion of the semiconductor material having n-type polarity are in contact.

5. The device of claim 1 , wherein the solution is comprised of an organic material.

Assignees

• Palo Alto Res Ct Inc

Inventors

• Ng Tse Nga
• Schwartz David Eric
• Veres Janos

Classifications

• H10D30/6733

  Multi-gate TFTs · CPC title

• H10K10/482 Primary

  the IGFET comprising multiple separately-addressable gate electrodes · CPC title

• H01L29/78645

  Electricity · mapped topic

• H01L51/0554 Primary

  Electricity · mapped topic