Field effect transistor structure with gate structure having a wall and floor portions

Patent metadata

Field	Value
Publication number	US-9843007-B2
Application number	US-201615225841-A
Country	US
Kind code	B2
Filing date	Aug 2, 2016
Priority date	Apr 28, 2016
Publication date	Dec 12, 2017
Grant date	Dec 12, 2017

Abstract

A field effect transistor (FET) structure includes a substrate, an internal gate, an insulation layer, a semiconductor strip, a gate dielectric insulator, and a gate conductor. The internal gate includes a floor portion located on the substrate and a wall portion extending from the floor portion. The insulation layer is located on the floor portion of the internal gate. The semiconductor strip is located on the wall portion and a portion of the insulation layer, and the semiconductor strip includes source/drain regions and a channel region adjacent to the source/drain regions. The gate dielectric insulator is located on the channel region. The gate conductor is located on the gate dielectric insulator.

First claim

What is claimed is:

1. A field effect transistor structure comprising:
a substrate;
an internal gate comprising a floor portion located on the substrate and a wall portion extending from the floor portion;
an insulation layer located on the floor portion of the internal gate;
a semiconductor strip located on the wall portion and a portion of the insulation layer, the semiconductor strip comprising source/drain regions and a channel region adjacent to the source/drain regions;
a gate dielectric insulator located on the channel region;
a gate conductor located on the gate dielectric insulator; and
a contact pillar connected to the floor portion of the internal gate.

2. The field effect transistor structure of claim 1 , wherein the wall portion comprises a semiconductor, a conductor, or an insulator.

3. The field effect transistor structure of claim 1 , wherein the semiconductor strip comprises a first semiconductor layer and a second semiconductor layer located on the first semiconductor layer, and a conductivity type of the first semiconductor layer is different from a conductivity type of the second semiconductor layer.

4. The field effect transistor structure of claim 3 , wherein the insulation layer is replaced by a third semiconductor layer with a conductivity type different with the conductivity type of the first semiconductor layer for forming a pn junction.

5. The field effect transistor structure of claim 3 , wherein the first semiconductor layer in the channel region is an inverted-U shaped structure, and the wall portion extends into the inverted-U shaped structure from the floor portion.

6. The field effect transistor structure of claim 3 , wherein the semiconductor strip further comprises a third semiconductor layer different from the second semiconductor layer, and the third semiconductor layer is located on the second semiconductor layer.

7. The field effect transistor structure of claim 1 , wherein the substrate comprises a semiconductor or a conductor.

8. The field effect transistor structure of claim 1 , wherein the substrate comprises metal.

9. The field effect transistor structure of claim 1 , wherein the internal gate comprises a conductive poly-semiconductor, an amorphous semiconductor, or a single crystal material.

10. The field effect transistor structure of claim 1 , wherein the internal gate comprises a conductive material.

11. The field effect transistor structure of claim 10 , wherein the charge trapping layer comprises Zr x Hf y Sr z SiO 3 , metal, a semiconductor, nano-dot metal, or an insulator, the polar ferroelectric layer comprises Li x Hf y Zr z O 3 , Pb x Ba y Sr z TiO 3 , Li x K y Ta z NbO 3 , La x Sr y Ba z MnO 3 , Zr x Hf y Sr z SiO 3 , Ba x La y Sr z Fe r O 3 , Ba x La y Sr z NiO 3 , or Ba x La y Sr z CoO 3 , 0≦x≦1, 0≦y≦1, 0≦z≦1, and 0≦r≦1.

12. The field effect transistor structure of claim 1 , wherein the gate dielectric insulator comprises a dielectric layer located on the channel region and a polar ferroelectric layer located on the dielectric layer, and the polar ferroelectric layer achieves a negative capacitance effect.

13. The field effect transistor structure of claim 1 , wherein the gate dielectric insulator comprises a polar ferroelectric layer and a charge trapping layer, locations of the polar ferroelectric layer and the charge trapping layer are exchangeable, and the field effect transistor structure acts as a non-volatile memory.

14. The field effect transistor structure of claim 1 , wherein the gate dielectric insulator comprises a charge trapping layer and a polar ferroelectric layer successively formed on the charge trapping layer, and the field effect transistor structure acts as a non-volatile memory.

15. The field effect transistor structure of claim 14 , wherein the charge trapping layer is composed by a layer of metal, semiconductor, or dielectric.

16. The field effect transistor structure of claim 15 , wherein the field effect transistor structure is a nano-dot memory.

17. The field effect transistor structure of claim 1 , wherein the substrate is a p-type substrate, the internal gate is an n-type conductor, the semiconductor strip comprises a p-type semiconductor layer located above the internal gate and an n-type semiconductor layer located on the p-type semiconductor layer, the p-type substrate and the p-type semiconductor layer comprise a material selected from the group consisting of (poly(3-alkylthiophene)), (poly(9,9-dioctylfluorene-co-bithiophene)), tetracene, pentacene, hexacene, and anthracene, and the n-type semiconductor layer comprises a material selected from the group consisting of naphthalene carbodiimide, perylene tetracarboxylic diimide, and fluorocarbon-substituted thiophene.

18. The field effect transistor structure of claim 1 , wherein the substrate is an n-type substrate, the internal gate is a p-type conductor, the semiconductor strip comprises an n-type semiconductor layer located above the internal gate and a p-type semiconductor layer located on the n-type semiconductor layer, the p-type semiconductor layer comprises a material selected from the group consisting of (poly(3-alkylthiophene)), (poly(9,9-dioctylfluorene-co-bithiophene)), tetracene, pentacene, hexacene, and anthracene, and the n-type substrate and the n-type semiconductor layer comprise a material selected from the group consisting of naphthalene carbodiimide, perylene tetracarboxylic diimide, and fluorocarbon-substituted thiophene.

Assignees

• Univ National Chiao Tung

Inventors

• Chang Chun-Yen

Classifications

• H01L51/0516

  Electricity · mapped topic

• H01L51/0529

  Electricity · mapped topic

• H01L51/0554 Primary

  Electricity · mapped topic

• H01L51/107

  Electricity · mapped topic

• H01L51/0562

  Electricity · mapped topic